IP Library Granted Patent US 8,306,035
Granted Patent B2
US 8,306,035 · App. 11/720,860 · Granted Nov 6, 2012

Communication circuit and method therefor

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Quick Facts
Patent No.
US 8,306,035
App. No.
11/720,860
Granted
Nov 6, 2012
Kind
B2
Abstract

In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Claims (28)

1. A communication circuit comprising:

the communication circuit having a receiver circuit having an input configured to receive a communication signal, the communication signal having a communication protocol that has a first signal level, a second signal level that is less than the first signal level, and a third signal level that is less than the second signal level; and

the communication protocol having at least two different types of communication frames wherein each communication frame has a frame identifier that specifies a type of communication frame followed by an information cell having information for the communication frame wherein a time duration of the information cell is not synchronous and is variable and wherein a first communication frame identifier includes a signal having one of the first signal level or the third signal level subsequent to having the second signal level and wherein a second communication frame identifier always includes a signal having a signal level that is the other one of the first or third signal level subsequent to having the second signal level.

2. The communication circuit of claim 1 wherein the information for the communication frame has a variable number of information cells.

3. The communication circuit of claim 1 wherein the second signal level is approximately half way between a value of an input voltage to the communication system and a return voltage of the communication system.

4. The communication circuit of claim 1 wherein the second signal level is approximately half way between the first signal level and the third signal level.

5. The communication circuit of claim 1 wherein a time that the signal is at either of the first signal level or the second signal level for an information cell is variable.

6. The communication circuit of claim 1 wherein a logical state of the signal is not time dependent.

7. The communication circuit of claim 1 wherein the two different types of communication frames include an address frame wherein the information for the address frame represents an address of a receiving circuit.

8. The communication circuit of claim 7 wherein the information for the address frame represents an address of a control circuit within the receiving circuit.

9. The communication circuit of claim 1 wherein the communication protocol includes a first type of communication frame of the two different types of communication frames followed by a second type of communication frame of the two different types of communication frames.

10. The communication circuit of claim 9 wherein an inter-frame spacing separates the first type of communication frame from the second type of communication frame.

11. A method of forming a communication circuit comprising:

configuring the communication circuit to receive a communications protocol having a signal that has a first signal level, a second signal level that is a lower level that the first signal level, and a third signal level that is a lower level that the second signal level;

configuring the communication circuit to use a first occurrence of the first signal level after an occurrence of the second signal level as an identifier of a first frame type wherein subsequent occurrences of the first signal level or the third signal level prior to an occurrence of the second signal level represent information for the first frame type; and

configuring the communication circuit to use a first occurrence of the third signal level after an occurrence of the second signal level as an identifier of a second frame type wherein subsequent occurrences of the first signal level or the third signal level prior to an occurrence of the second signal level represent information for the second frame type.

12. The method of claim 11 further including configuring the communication circuit to use the second signal level as an end of both the first frame type and the second frame type.

13. The method of claim 12 wherein configuring the communication circuit to use the first occurrence of the first signal level after the occurrence of the second level signal includes configuring the communication circuit to use the first occurrence of the first signal level after the occurrence of the second signal level to represent a destination for the second frame type.

14. The method of claim 13 includes configuring the communication circuit to use the information for the second frame type as data for the destination.

15. The method of claim 11 wherein configuring the communication circuit to use the first occurrence of the first signal level after the occurrence of the second signal level includes configuring the communication circuit to use the first occurrence of the first signal level after the occurrence of the second signal level to represent a destination that is one of a register of a receiving circuit or one circuit of a plurality of circuits.

16. A communication circuit comprising:

a semiconductor device configured to operate with a communication protocol having a first signal level, a second signal level that is less than the first signal level, and a third signal level that is less than the second signal level; and

the communication protocol having a communication frame that includes a frame identifier and frame information, the communication protocol using a first occurrence of the first or third signal level after an occurrence of the second signal level as an identifier of a frame type and wherein the frame information includes at least one of either the first signal level or the third signal level for a first time period following an occurrence of the second signal level and wherein the first time period is variable.

17. The communication circuit of claim 16 wherein the frame information includes, for a second time period, at least one of either the first signal level or the third signal level wherein the second time period is variable.

18. A communication circuit comprising:

a semiconductor device configured to receive a communication signal on a single input of the semiconductor device, the semiconductor device having a communication receiver circuit that includes a control block wherein the control block is replaceable to accept different communication protocols and to control operation of the communication receiver circuit to responsively to the communication protocol; and

the communication protocol having an address frame and a data frame and a time-out period between transitions of the address and date frames wherein the control block sets an operating mode of the communication receiver circuit after the time-out period and wherein the time-out period is variable.

19. The method of claim 11 further including configuring the communication circuit to receive the signal wherein the signal is devoid of the second signal level for multiple occurrences of the first or third signal level after the first occurrence of the first or third signal level.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →