IP Library Granted Patent US 7,796,600
Granted Patent B2
US 7,796,600 · App. 11/755,062 · Granted Sep 14, 2010

Compact MPE-FEC erasure location cache memory for DVB-H receiver

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Quick Facts
Patent No.
US 7,796,600
App. No.
11/755,062
Granted
Sep 14, 2010
Kind
B2
Abstract

Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2 M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

Claims (48)

1. A method of identifying erasure locations in transmitted data received by a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

grouping data bytes from Internet Protocol (IP) datagrams in a Multi-Protocol Encapsulator Forward Error Correction Random Access Memory (MPE-FEC RAM) unit in a column-wise manner into data blocks comprising 2 M consecutive bytes per data block, wherein M comprises a positive integer;

using an erasure cache RAM comprising a size of 2 (10−M) ×255 entries having (M+2) bits per entry to indicate an erasure status of each data byte in a MPE data frame;

using M bits in the (M+2)-bit entry in said erasure cache RAM to identify a 2 M −1 potential boundary of said IP datagrams when a corresponding data block covers two said IP datagrams; and

using a remaining two bits in said (M+2)-bit entry to identify potential erasure location conditions in said IP datagrams.

2. The method of claim 1 , wherein said MPE-FEC RAM comprises 2 (10−M) ×255 data blocks per said MPE data frame.

3. The method of claim 1 , wherein 2 M is no larger than a smallest IP datagram length such that each said data block of 2 M bytes comprises data from at most two said IP datagrams.

4. The method of claim 1 , wherein a size of said erasure cache RAM comprises at most 32 Kbits.

5. The method of claim 1 , wherein said potential erasure location conditions comprises:

a first condition where both of said two said IP datagrams are error free;

a second condition where only a first one of said two said IP datagrams has errors;

a third condition where only a second one of said two said IP datagrams has errors; and

a fourth condition where said both of said two IP datagrams have errors.

6. The method of claim 5 , wherein in said first condition, no erasures exist in the 2 M byte data block.

7. The method of claim 5 , wherein in said second condition, all said data bytes before a corresponding IP datagram boundary are marked as erasures.

8. The method of claim 5 , wherein in said third condition, all said data bytes after a corresponding IP datagram boundary are marked as erasures.

9. The method of claim 5 , wherein in said fourth condition, all said data bytes in a corresponding data block is marked as an erasure.

10. The method of claim 1 , wherein said M bits in said (M+2)-bit entry is used to indicate whether a corresponding data block covers data from exactly one IP datagram.

11. The method of claim 5 , wherein said two bits in said (M+2)-bit entry is used to indicate the first, second, third, and fourth conditions.

12. A method of identifying erasure locations in transmitted data received by a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

grouping data bytes from Internet Protocol (IP) datagrams in a Multi-Protocol Encapsulator Forward Error Correction Random Access Memory (MPE-FEC RAM) unit in a column-wise manner into data blocks comprising 2 M consecutive bytes per data block, wherein M comprises a positive integer;

using an erasure cache RAM comprising a size of 2 (10−M) ×255 entries having (M+1) bits per entry to indicate an erasure status of each data byte in a MPE data frame;

using M bits in the (M+1)-bit entry in said erasure cache RAM to identify a 2 M −1 potential boundary of said IP datagrams when a corresponding data block covers two said IP datagrams with a different cycle redundancy check (CRC) matching status; and

using a remaining one bit in said (M+1)-bit entry to identify potential erasure location conditions in said IP datagrams.

13. The method of claim 12 , wherein said MPE-FEC RAM comprises 2 (10−M) ×255 data blocks per said MPE data frame.

14. The method of claim 12 , wherein 2 M is no larger than a smallest IP datagram length such that each said data block of 2 M bytes comprises data from at most two said IP datagrams.

15. The method of claim 12 , wherein a size of said erasure cache RAM comprises at most 28 Kbits.

16. The method of claim 12 , wherein said potential erasure location conditions comprises:

a first condition where only a first one of said two said IP datagrams has errors; and

a second condition where only a second one of said two said IP datagrams has errors.

17. The method of claim 16 , wherein in said first condition, all said data bytes before a corresponding IP datagram boundary are marked as erasures.

18. The method of claim 16 , wherein in said second condition, all said data bytes after a corresponding IP datagram boundary are marked as erasures.

19. The method of claim 12 , wherein said M bits in said (M+1)-bit entry is used to indicate whether a corresponding data block covers data from exactly one IP datagram or covers two datagrams of the same CRC matching status.

20. The method of claim 16 , wherein said remaining one bit in said (M+1)-bit entry is used to indicate the first and second conditions for a corresponding data block.

21. A method of identifying erasure locations in transmitted data received by a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

grouping data bytes from Internet Protocol (IP) datagrams in a Multi-Protocol Encapsulator Forward Error Correction Random Access Memory (MPE-FEC RAM) unit in a column-wise manner into data blocks comprising 2 M consecutive bytes per data block, wherein M comprises a positive integer;

using an erasure cache RAM comprising a size of 2 (10−M) ×255 entries having only one bit per entry to indicate an erasure status of each data byte in an entire data block; and

using said only one bit to identify potential erasure location conditions in said IP datagrams.

22. The method of claim 21 , wherein when a particular data block covers more than one IP datagram and there are cycle redundancy check (CRC) mismatches in any of the IP datagrams, then said particular data block is marked as an erasure.

23. The method of claim 22 , wherein when said particular data block is not marked as an erasure, then said particular data block is marked as error free.

24. The method of claim 21 , wherein when said M equals 4, a size of said erasure cache RAM per MPE frame equals 16K.

25. The method of claim 21 , wherein when said M equals 5, a size of said erasure cache RAM per MPE frame equals 8K.

26. The method of claim 21 , wherein when said M equals 6, a size of said erasure cache RAM per MPE frame equals 4K.

27. The method of claim 23 , further comprising using said only one bit to identify two possible erasure statuses of a corresponding data block.

28. A lossless method of identifying erasure locations in transmitted data received by a Digital Video Broadcasting over Handheld (DVB-H) receiver, said method comprising:

grouping data bytes from Internet Protocol (IP) datagrams in a Multi-Protocol Encapsulator Forward Error Correction Random Access Memory (MPE-FEC RAM) unit in a column-wise manner into data blocks comprising 2 M consecutive bytes per data block, wherein M comprises a positive integer;

using an erasure cache RAM comprising a size of 2 (10−M) ×255 entries having (M+1) bits per entry to indicate an erasure status of each data byte in a MPE data frame; and

using (M+1)-bit binary encoding to represent 2 (M+1) erasure patterns, wherein the erasure patterns occur when a corresponding data block covers one or two of said IP datagrams.

Assignments (31)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 6, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL WIRELESS MCU TECHNOLOGIES CORPORATION
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 6, 2016
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To: NEWPORT MEDIA, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 034705/0090 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: BRIDGE BANK, NATIONAL ASSOCIATION
To: ATMEL CORPORATION
Reel/Frame 033907/0517 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: PINNACLE VENTURES, L.L.C.
To: ATMEL CORPORATION
Reel/Frame 033908/0435 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: PINNACLE VENTURES, L.L.C.
To: ATMEL CORPORATION
Reel/Frame 033908/0379 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 033908/0242 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 033907/0775 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
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TERMINATION OF SECURITY Recorded Oct 7, 2014
From: HORIZON TECHNOLOGY FINANCE CORPORATION
To: ATMEL CORPORATION
Reel/Frame 033907/0702 →
PATENT SECURITY AGREEMENT Recorded Sep 5, 2014
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PATENT SECURITY AGREEMENT Recorded Sep 5, 2014
From: ATMEL WIRELESS MCU TECHNOLOGIES CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 1, 2013
From: NEWPORT MEDIA, INC.
To: HORIZON TECHNOLOGY FINANCE CORPORATION, AS COLLATERAL AGENT
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From: NEWPORT MEDIA, INC., A DELAWARE CORPORATION; NEWPORT MEDIA, INC., A CALIFORNIA CORPORATION
To: PINNACLE VENTURES, L.L.C.
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SECURITY AGREEMENT Recorded Dec 31, 2012
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To: BRIDGE BANK, NATIONAL ASSOCIATION
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SECURITY AGREEMENT Recorded May 31, 2012
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2007
From: CHEN, CHAOLIANG T.; DENK, TRACY; YOUSEF, NABIL R.; TREIGHERMAN, PHILIP
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