Method of making a wafer level integration package
View Patent ↗A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad, electrically connecting a die to a second surface of the first electrical contact pad, cutting the wafer to form a channel portion and a connecting portion, disposing an encapsulant over the die and the channel portion, backgrinding the wafer to remove the connecting portion and expose a surface of the through-hole interconnection, disposing a second electrical contact pad over the surface of the through-hole interconnection, disposing a dielectric layer along a side surface of the second electrical contact pad, and singulating the wafer into an individual segment containing the die. The dielectric layer is disposed to form a plurality of lands extending across a bottom surface of the semiconductor device.
1. A method of forming a semiconductor package, comprising:
providing a wafer having a first electrical contact pad integrated into a top surface of the wafer;
forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad;
electrically connecting a die to a second surface of the first electrical contact pad;
cutting the wafer to form a channel portion and a connecting portion;
disposing an encapsulant over the die and the channel portion;
backgrinding the wafer to remove the connecting portion and expose a surface of the through-hole interconnection;
disposing a second electrical contact pad over the surface of the through-hole interconnection; and
disposing a dielectric layer along a side surface of the second electrical contact pad.
2. The method of claim 1 , further including disposing a solder bump between the die and the first electrical contact pad to electrically connect the die to the first electrical contact pad.
3. The method of claim 1 , further including disposing an underfill material between the die and the first electrical contact pad to provide structural support.
4. The method of claim 1 , further including connecting a solder ball to the second electrical contact pad to provide electrical connectivity.
5. The method of claim 4 , further including testing the die for functionality.
6. The method of claim 4 , further including singulating the wafer into an individual segment containing the die.
7. The method of claim 1 , wherein the die includes a flip chip semiconductor device, a wire bond semiconductor device, a passive component, or a combination thereof.
8. The method of claim 1 , wherein the dielectric layer is disposed to form a plurality of lands extending across a bottom surface of the semiconductor device.
9. The method of claim 1 , further including electrically connecting a passive component to the first surface of the first electrical contact pad.
10. A method of manufacturing a semiconductor device, comprising:
providing a wafer having a first electrical contact pad integrated into a top surface of the wafer;
providing a through-hole interconnection extending downward from a first surface of the first electrical contact pad;
providing a die electrically connected to a second surface of the first electrical contact pad;
providing a second electrical contact pad disposed over a surface of the through-hole interconnection; and
providing a dielectric layer disposed along a side surface of the second electrical contact pad, wherein:
the wafer is cut to form a channel portion and a connecting portion,
an encapsulant is disposed over the die and the channel portion, and
the wafer is backgrinded to remove the connecting portion and expose the surface of the through-hole interconnection.
11. The method of manufacture of claim 10 , further including providing a solder bump disposed between the die and the first electrical contact pad to electrically connect the die to the first electrical contact pad.
12. The method of manufacture of claim 10 , further including providing an underfill material disposed between the die and the first electrical contact pad to provide structural support.
13. The method of manufacture of claim 10 , wherein the die includes a flip chip semiconductor device, a wire bond semiconductor device, a passive component, or a combination thereof.
14. The method of manufacture of claim 10 , wherein the dielectric layer is disposed in a pattern to render a plurality of lands extending across a bottom surface of the semiconductor device.
15. The method of manufacture of claim 10 , further including providing a passive component electrically connected to the first surface of the first electrical contact pad.
16. The method of manufacture of claim 10 , wherein the encapsulant is disposed such that a top surface of the die is exposed.
17. The method of manufacture of claim 16 , further including providing an adhesive layer disposed over the top surface of the die, and a heat spreader structure disposed over the adhesive to render a thermally enhanced semiconductor package.