IP Library Granted Patent US 7,800,211
Granted Patent B2
US 7,800,211 · App. 11/771,086 · Granted Sep 21, 2010

Stackable package by using internal stacking modules

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Quick Facts
Patent No.
US 7,800,211
App. No.
11/771,086
Granted
Sep 21, 2010
Kind
B2
Abstract

A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer.

Claims (46)

1. A semiconductor package, comprising:

a first substrate having a plurality of solder balls;

a first semiconductor die mounted to the first substrate;

a first double side mold (DSM) internal stackable module (ISM) in physical contact with the first semiconductor die through a first adhesive to reduce a height of the semiconductor package, the first DSM ISM including,

(a) a second substrate having first and second cavities,

(b) a second semiconductor die disposed in the first cavity of the second substrate,

(c) a third semiconductor die disposed in the second cavity of the second substrate, and

(d) a platform disposed between the second semiconductor die and third semiconductor die and extending beyond the second substrate, the second semiconductor die being electrically connected to the third semiconductor die through conductive traces formed in the platform;

a first electrical contact connecting the first semiconductor die to a first one of the plurality of solder balls; and

a second electrical contact connecting the platform to a second one of the plurality of solder balls, wherein the second electrical contact is a solder ball.

2. The semiconductor package of claim 1 , further including a second DSM ISM in physical contact with the first DSM ISM through a second adhesive, the second DSM ISM including fourth and fifth semiconductor die disposed in the second DSM ISM.

3. The semiconductor package of claim 1 , further including a third electrical contact coupled between a platform extending from the second DSM ISM and a third one of the plurality of solder balls.

4. The semiconductor package of claim 1 , further including an encapsulant surrounding the first semiconductor die and first DSM ISM.

5. The semiconductor package of claim 4 , further including an interposer disposed above the first DSM ISM, the interposer being electrically connected to the platform of the first DSM ISM.

6. The semiconductor package of claim 5 , further including an exposed mold area in the encapsulant above the interposer.

7. A semiconductor package, comprising:

a first substrate;

a first semiconductor die mounted to the first substrate;

a first double side mold (DSM) internal stackable module (ISM) in physical contact with the first semiconductor die through a first adhesive to reduce a height of the semiconductor package, the first DSM ISM including,

(a) a second substrate having first and second cavities,

(b) a second semiconductor die disposed in the first cavity of the second substrate,

(c) a third semiconductor die disposed in the second cavity of the second substrate, and

(d) a platform disposed between the second semiconductor die and third semiconductor die and extending beyond the second substrate;

a second DSM ISM in physical contact with the first DSM ISM through a second adhesive, the second DSM ISM including fourth and fifth semiconductor die disposed in the second DSM ISM;

a first electrical connection coupled between the first semiconductor die and first substrate; and

a second electrical connection coupled between the platform and first substrate.

8. The semiconductor package of claim 7 , wherein the second semiconductor die is electrically connected to the third semiconductor die through conductive traces formed in the platform.

9. The semiconductor package of claim 7 , wherein the second electrical contact includes a bond wire or solder bump.

10. The semiconductor package of claim 7 , further including an encapsulant deposited over the first semiconductor die and first DSM ISM.

11. The semiconductor package of claim 7 , further including an interposer disposed over the first DSM ISM, the interposer being electrically connected to the platform.

12. A semiconductor package, comprising:

a first substrate;

a first semiconductor die mounted to the first substrate;

a first double side mold (DSM) internal stackable module (ISM) in physical contact with the first semiconductor die through a first adhesive to reduce a height of the semiconductor package;

a second DSM ISM in physical contact with the first DSM ISM through a second adhesive, the second DSM ISM including fourth and fifth semiconductor die disposed in the second DSM ISM;

a first electrical connection coupled between the first semiconductor die and first substrate; and

a second electrical connection coupled between the first DSM ISM and first substrate.

13. The semiconductor package of claim 12 , wherein the first DSM ISM includes:

a second substrate having first and second cavities;

a second semiconductor die disposed in the first cavity of the second substrate;

a third semiconductor die disposed in the second cavity of the second substrate; and

a platform disposed between the second semiconductor die and third semiconductor die and extending beyond the second substrate.

14. The semiconductor package of claim 13 , wherein the second semiconductor die is electrically connected to the third semiconductor die through conductive traces formed in the platform.

15. The semiconductor package of claim 12 , wherein the second electrical contact includes a bond wire or solder bump.

16. The semiconductor package of claim 12 , further including an encapsulant deposited over the first semiconductor die and first DSM ISM.

17. The semiconductor package of claim 12 , further including an interposer disposed over the first DSM ISM, the interposer being electrically connected to the platform.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0309. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 11, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0767 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0309 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2007
From: YANG, JOUNGIN; KANG, KEONTEAK; KIM, YOUNGCHUL; YIM, CHOONGBIN
To: STATS CHIPPAC, LTD.
Reel/Frame 019498/0638 →