IP Library Granted Patent US 8,018,052
Granted Patent B2
US 8,018,052 · App. 11/772,044 · Granted Sep 13, 2011

Integrated circuit package system with side substrate having a top layer

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,018,052
App. No.
11/772,044
Granted
Sep 13, 2011
Kind
B2
Abstract

An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.

Claims (41)

1. A method for manufacturing an integrated circuit package system comprising:

providing a package substrate;

attaching an integrated circuit over the package substrate;

applying a fill layer between the integrated circuit and the package substrate;

attaching a side substrate having side substrate traces and a substrate connector, adjacent the integrated circuit and over the package substrate with the substrate connector on the package substrate, and leaving an unfilled gap between the integrated circuit and the side substrate, unfilled by the fill layer;

aligning a side substrate outer edge with a package substrate outer edge; and

attaching a heat spreader to the side substrate with a substrate attach layer.

2. The method as claimed in claim 1 wherein aligning the side substrate outer edge with the package substrate outer edge includes aligning along a vertical plane.

3. The method as claimed in claim 1 wherein attaching the side substrate includes attaching the side substrate having a circuit device.

4. The method as claimed in claim 1 wherein attaching the side substrate includes attaching the side substrate having side substrate traces.

5. The method as claimed in claim 1 wherein attaching the side substrate includes attaching the side substrate having a conductive layer substantially exposed.

6. A method for manufacturing an integrated circuit package system comprising:

providing a package substrate having package substrate traces;

attaching an integrated circuit over the package substrate;

applying a fill layer between the integrated circuit and the package substrate;

attaching a side substrate having side substrate traces and a substrate connector over a perimeter of the package substrate and adjacent to the integrated circuit with the integrated circuit connected to the package substrate traces and the side substrate traces, and leaving an unfilled gap between the integrated circuit and the side substrate, unfilled by the fill layer;

aligning a side substrate outer edge with a package substrate outer edge; and

attaching a heat spreader over the side substrate and the integrated circuit on a side opposite the package substrate with a substrate attach layer.

7. The method as claimed in claim 6 wherein aligning the side substrate outer edge with the package substrate outer edge includes aligning along a vertical plane.

8. The method as claimed in claim 6 wherein attaching the side substrate includes attaching the side substrate having a circuit device connected to the side substrate traces.

9. The method as claimed in claim 6 wherein attaching the side substrate includes attaching the side substrate having side substrate traces for distributed signal lines.

10. The method as claimed in claim 6 wherein attaching the side substrate includes attaching the side substrate having a conductive layer substantially exposed on a side substrate second surface opposite the package substrate.

11. An integrated circuit package system comprising:

a package substrate;

an integrated circuit over the package substrate;

a fill layer is between the integrated circuit and the package substrate and leaves an unfilled gap between the integrated circuit and the side substrate;

a side substrate having side substrate traces and a substrate connector, adjacent the integrated circuit and over the package substrate with the substrate connector on the package substrate and the side substrate having side substrate traces over a perimeter of the package substrate;

a side substrate outer edge aligned with a package substrate outer edge; and

a heat spreader attached to the side substrate with a substrate attach layer.

12. The system as claimed in claim 11 wherein the side substrate outer edge and the package substrate outer edge align along a vertical plane.

13. The system as claimed in claim 11 wherein the side substrate includes the side substrate having a circuit device.

14. The system as claimed in claim 11 wherein the side substrate includes the side substrate having side substrate traces.

15. The system as claimed in claim 11 wherein the side substrate includes the side substrate having a conductive layer substantially exposed.

16. The system as claimed in claim 11 wherein:

the package substrate has package substrate traces;

the integrated circuit is adjacent the side substrate over the package substrate, the integrated circuit connected to the package substrate traces and the side substrate traces; and

the heat spreader over the side substrate and the integrated circuit on a side opposite the package substrate.

17. The system as claimed in claim 16 wherein the side substrate outer edge and the package substrate outer edge align along a vertical plane.

18. The system as claimed in claim 16 wherein the side substrate includes the side substrate having a circuit device connected to the side substrate traces.

19. The system as claimed in claim 16 wherein the side substrate includes the side substrate having side substrate traces for distributed signal lines.

20. The system as claimed in claim 16 wherein the side substrate includes the side substrate having a conductive layer substantially exposed on a side substrate second surface opposite the package substrate.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0301. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064913/0352 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0301 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2011
From: KIM, KYUNGOE; KANG, TAEWOO; SHIN, HYUNSU
To: STATS CHIPPAC LTD.
Reel/Frame 026528/0038 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2007
From: KIM, KYUNGOE; KANG, TAEWOO; SHIN, HYUNSU
To: STATS CHIPPAC LTD.
Reel/Frame 019502/0052 →
Continuity (1)
Related Publication 20090001545A1 · Jan 1, 2009