IP Library Granted Patent US 7,824,956
Granted Patent B2
US 7,824,956 · App. 11/772,082 · Granted Nov 2, 2010

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

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Quick Facts
Patent No.
US 7,824,956
App. No.
11/772,082
Granted
Nov 2, 2010
Kind
B2
Abstract

In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a reversible resistance-switching element above the first conductor using a selective growth process; (3) forming a diode above the first conductor; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.

Claims (43)

1. A method of forming a memory cell comprising:

forming a steering element above a substrate; and

forming a reversible resistance-switching element coupled to the steering element, wherein the reversible resistance-switching element is formed using a selective growth process comprising forming a Ti-nitride containing layer, etching the titanium nitride containing layer and oxidizing the etched Ti-nitride containing layer.

2. The method of claim 1 wherein forming the steering element comprises forming a diode.

3. The method of claim 1 wherein forming the steering element comprises forming a polycrystalline diode.

4. The method of claim 1 wherein forming the steering element comprises forming a vertical polycrystalline diode.

5. The method of claim 1 wherein forming the steering element comprises forming a vertical polycrystalline diode having polycrystalline material that is in a low-resistivity state.

6. The method of claim 1 wherein forming the steering element comprises forming a p-n diode or a p-i-n.

7. The method of claim 1 wherein forming the steering element comprises forming a thin film transistor.

8. The method of claim 1 wherein forming the steering element comprises forming a thin film, metal oxide semiconductor field effect transistor (MOSFET).

9. The method of claim 1 wherein forming the reversible resistance-switching element comprises forming at least one of TiO, TiO 2 , TiO x and TiO x N y .

10. The method of claim 9 wherein forming the reversible resistance-switching element comprises forming a reversible resistance-switching element having an oxide thickness of about 500 angstroms or less.

11. The method of claim 10 wherein forming the reversible resistance-switching element comprises forming a reversible resistance-switching element having an oxide thickness of about 300 angstroms or less.

12. The method of claim 1 wherein the Ti-containing layer comprises a TiN layer.

13. The method of claim 1 further comprising coupling the steering element and reversible resistance-switching element in series.

14. A memory cell formed using the method of claim 1 .

15. A memory cell formed using the method of claim 9 .

16. A method of forming a memory cell comprising:

forming a first conductor above a substrate;

forming a reversible resistance-switching element above the first conductor, wherein the reversible resistance-switching element is formed using a selective growth process comprising forming a Ti-nitride containing layer, etching the Ti-nitride containing layer, and oxidizing the etched Ti-nitride containing layer;

forming a diode above the first conductor; and

forming a second conductor above the diode and the reversible resistance-switching element.

17. The method of claim 16 wherein forming the diode comprises forming a vertical polycrystalline diode.

18. The method of claim 17 further comprising forming a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.

19. The method of claim 16 wherein forming the reversible resistance-switching element comprises selectively forming at least one of TiO, TiO 2 , TiO x and TiO x N y .

20. The method of claim 16 wherein the Ti-containing layer comprises a TiN layer.

21. A memory cell formed using the method of claim 16 .

22. A memory cell formed using the method of claim 19 .

23. A method of forming a memory cell comprising:

forming a first conductor above a substrate;

forming a titanium nitride layer above the first conductor;

selectively forming a reversible resistance-switching element by etching the titanium nitride layer, and oxidizing the etched titanium nitride layer;

forming a vertical polycrystalline diode above the reversible resistance-switching element; and

forming a second conductor above the vertical polycrystalline diode.

24. The method of claim 23 further comprising forming a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.

25. The method of claim 23 wherein forming the reversible resistance-switching element comprises selectively forming at least one of TiO, TiO 2 , TiO x and TiO x N y .

26. The method of claim 23 wherein selectively forming the reversible resistance-switching element comprises forming a reversible resistance-switching element having an oxide thickness of about 300 angstroms or less.

27. The method of claim 23 wherein forming the vertical polycrystalline diode comprises forming a vertical polysilicon diode.

28. A memory cell formed using the method of claim 23 .

29. The method of claim 1 wherein forming the reversible resistance-switching element comprises forming at least one of Ta 2 O 5 , Nb 2 O 5 , Al 2 O 3 , HfO 2 , and V 2 O 5 .

30. A method of forming a memory cell, the method comprising:

forming a steering element above a substrate; and

forming a reversible resistance-switching element coupled to the steering element, wherein the reversible resistance-switching element comprises an etched and oxidized Ti-nitride material.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2025
From: SANDISK TECHNOLOGIES, INC.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 070778/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038809/0600 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2007
From: SCHRICKER, APRIL; HERNER, BRAD; CLARK, MARK
To: SANDISK 3D, LLC
Reel/Frame 019848/0113 →