Vertical MOS transistor and method therefor
View Patent ↗In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.
1. A vertical MOS transistor comprising:
a bulk semiconductor substrate of a first conductivity type having a drain conductor on a first surface and having a second surface that is opposite to the first surface;
an epitaxial layer of the first conductivity type on the second surface of the bulk semiconductor substrate;
a first doped region of a second conductivity type on the epitaxial layer, the first doped region having a first outside edge extending from near the surface of the epitaxial layer into the epitaxial layer;
a thin insulator on a portion of the epitaxial layer, a first portion of the thin insulator overlying a portion of the first doped region and extending past the first outside edge of the first doped region to overly a portion of the epitaxial layer that is adjacent to the first outside edge of the first doped region;
a trench type gate formed on the epitaxial layer and extending into the first doped region, the trench type gate having a first gate conductor within a trench of the trench type gate;
a source formed as a second doped region of the first conductivity type on the epitaxial layer and within the first doped region, the source positioned adjacent to the trench type gate;
a second gate conductor on the first portion of the thin insulator and overlying a portion of the first doped region that is between the trench type gate and the first outside edge of the first doped region wherein the second gate conductor does not extend to overlie a P-N junction formed at an interface of the epitaxial layer and the first outside edge of the first doped region wherein the first outside edge of the first doped region does not underlie a thick field oxide region and wherein the second gate conductor does not overly a thick field oxide region;
an inter-layer dielectric formed on the first portion of the thin insulator and overlying a portion of the second gate conductor wherein the inter-layer dielectric has a thickness that is at least twice a thickness of the thin insulator, the inter-layer dielectric extending across the thin insulator past the first outside edge of the first doped region; and
a metal gate conductor formed on a portion of the inter-layer dielectric and on a portion of the second gate conductor.
2. The vertical MOS transistor of claim 1 wherein the first gate conductor is polysilicon that is within the trench and insulated from sidewalls of the trench by a gate insulator.
3. The vertical MOS transistor of claim 1 wherein the second gate conductor is positioned between the trench type gate and the first outside edge of the first doped region.
4. The vertical MOS transistor of claim 1 wherein the second gate conductor is positioned to not overly a depletion region formed at the interface of the epitaxial layer and the first outside edge of the first doped region.
5. The vertical MOS transistor of claim 1 wherein the second gate conductor is positioned at least one micron away from the interface of the epitaxial layer and the first outside edge of the first doped region.
6. The vertical MOS transistor of claim 1 further including a body contact positioned between the trench type gate and the second gate conductor.
7. The vertical MOS transistor of claim 1 wherein no elements of the vertical MOS transistor overlie a field oxide region.
8. The vertical MOS transistor of claim 1 further including a drain contact region formed as a third doped region on the epitaxial layer wherein the drain contact region is positioned within the epitaxial layer and a first distance from the first outside edge of the first doped region.
9. The vertical MOS transistor of claim 1 wherein the inter-layer dielectric is not formed by thermal oxidation.
10. A vertical MOS transistor comprising:
a semiconductor substrate of a first conductivity type having a first surface and having a drain conductor on a second surface that is opposite to the first surface;
a first doped region of a second conductivity type on the first surface, the first doped region having a first outside edge extending from near the first surface into the semiconductor substrate;
a thin insulator on a portion of the semiconductor substrate, a first portion of the thin insulator overlying a portion of the first doped region and extending past the first outside edge of the first doped region to overly a portion of the semiconductor substrate that is adjacent to the first outside edge of the first doped region;
a trench type gate extending into the first doped region, the trench type gate having a first gate conductor within a trench of the trench type gate;
a source formed as a second doped region of the first conductivity type on the semiconductor substrate and within the first doped region, the source positioned adjacent to the trench type gate;
a second gate conductor on the first portion of the thin insulator and overlying a portion of the first doped region that is between the trench type gate and the first outside edge of the first doped region wherein the second gate conductor does not overly a thick field oxide region; and
an inter-layer dielectric formed on the first portion of the thin insulator and overlying a portion of the second gate conductor, the inter-layer dielectric extending past the first outside edge of the first doped region wherein a thickness of the inter-layer dielectric is greater than a thickness of the thin insulator and wherein the inter-layer dielectric does not overlie a field oxide region.
11. The vertical MOS transistor of claim 10 wherein the first gate conductor is polysilicon that is within the trench and insulated from sidewalls of the trench by a gate insulator and wherein the second gate conductor is polysilicon.
12. The vertical MOS transistor of claim 10 wherein the inter-layer dielectric is not formed by thermal oxidation of the semiconductor substrate.
13. The vertical MOS transistor of claim 10 wherein the second gate conductor does not extend to overlie a P-N junction formed at an interface of the semiconductor substrate and the first outside edge of the first doped region.
14. The vertical MOS transistor of claim 10 further including a metal gate conductor formed on a portion of the inter-layer dielectric and on a portion of the second gate conductor.
15. The vertical MOS transistor of claim 1 wherein the vertical MOS transistor is devoid of a field oxide region overlying the first doped region.
16. The vertical MOS transistor of claim 1 wherein the vertical MOS transistor is devoid of a field oxide region.
17. The vertical MOS transistor of claim 1 wherein the vertical MOS transistor is devoid of a thick field oxide region in a termination region of the vertical MOS transistor.
18. The vertical MOS transistor of claim 10 wherein the vertical MOS transistor is devoid of a thick field oxide region overlying the first outside edge of the first doped region.
19. The vertical MOS transistor of claim 10 wherein the vertical MOS transistor is devoid of a thermally grown field oxide region.
20. The vertical MOS transistor of claim 10 wherein the vertical MOS transistor is devoid of a thick field oxide region in a termination region of the vertical MOS transistor.