Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
View Patent ↗A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
1. A method for manufacturing a memory device, comprising:
performing a shallow trench isolation process on a semiconductor material to form an active region and an isolation region;
forming a charge trapping structure over the active region, wherein the charge trapping structure is self-aligned;
separating charge trapping structures at their respective bottom portions;
forming a first layer of semiconductor or conductive material over the charge trapping structure;
wherein the trapping structure is self-aligned by depositing a non-conformal film layer over a charge trapping layer, wherein the non-conformal film layer forms a pinch-off or a channel and void region over an STI trench;
opening up the pinch-off or widening the channel by etch; and
completely or partially etching to separate the trapping structure layer between a plurality of cells for isolation in a subsequent top oxide step.
2. The method of claim 1 , further comprising:
forming an optional thin conformal sacrificial top oxide over the charge trapping layer before depositing the non-conformal film layer;
etching the thin sacrificial top oxide over the STI trench but leaving a thick residual oxide over the active region;
completely or partially etching to separate the trapping structure layer between a plurality of cells for isolation in a subsequent top oxide step.
3. The method of claim 1 , further comprising:
removing the non conformal layer and dipping off the optional oxide on the trapping layer;
forming a top oxide on trapping layer and converting the remaining trap layer to oxide to completely separate the trapping layer for each cell.
4. The method of claim 1 , wherein said non-conformal film comprises a polymer.
5. The method of claim 4 , wherein said polymer is deposited in a processing chamber using plasma and/or other means to deposit and/or etch thin films.
6. The method of claim 5 , wherein said polymer deposited by a combination selected from the group consisting of fluorocarbon gases, hydrocarbon gases, noble gases and other gases.
7. The method of claim 6 , wherein said fluorocarbon gases comprise CH3F said hydrocarbon comprises C2H4, and said other gases comprise HBr, Br2, HCl, Cl2, H2, or noble gases.
8. The method of claim 1 , wherein said non-conformal film comprises amorphous carbon.
9. The method of claim 8 , wherein said amorphous carbon or any hydrocarbon is deposited in a CVD chamber.
10. The method of claim 1 , wherein said non-conformal film comprises high density plasma oxide.
11. The method of claim 1 , wherein said non-conformal film comprises silane oxide.
12. The method of claim 1 , wherein said non-conformal film comprises low k oxide deposited using a PECVD tool.
13. The method of claim 1 , wherein said non-conformal film comprises a hydrocarbon with 1.5-3.5 dielectric constant.
14. The method of claim 1 , further comprising:
performing the shallow trench isolation process before forming the charge trapping structure to expose corners of the active region so that the exposed corners can be rounded through a rounding process.
15. The method of claim 1 , wherein forming the charge trapping structure comprises:
forming a bottom oxide layer over the active region;
forming a nitride layer over the first oxide layer; and
forming a top block oxide layer over the nitride layer.
16. The method of claim 5 , wherein the nitride layer is comprised of silicon rich nitride.
17. The method of claim 5 , wherein the nitride layer is comprised of nitride on top of silicon rich nitride.
18. The method of claim 5 , wherein the nitride layer is comprised of multiple layers of nitride having different percentages of silicon content.
19. The method of claim 1 further comprising:
fabricating a top oxide layer;
masking an ONO structure;
etching the ONO structure;
fabricating a first periphery gate oxide layer;
etching the periphery gate oxide layer;
fabricating a second periphery gate oxide layer, wherein the second periphery gate oxide layer is thinner than the first periphery gate oxide layer.
20. The method of claim 19 further comprising:
depositing polysilicon after the second periphery gate oxide layer;
defining word lines;
etching the top oxide layer and trapping layer between word lines.