Edge alignment for frequency synthesizers
View Patent ↗A frequency synthesizer ( 50, 70 ) including an edge-detection circuit ( 51, 60 ) for disabling elements of the frequency synthesizer ( 50, 70 ) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer ( 50, 70 ) and enables elements of the frequency synthesizer ( 50, 70 ) upon the detection of the transition edge.
1. A method of starting a frequency synthesizer that includes a program/swallow counter and a prescaler, comprising:
disabling elements, including the program/swallow counter and not the prescaler, of said frequency synthesizer prior to starting said frequency synthesizer;
detecting a transition edge of a reference-clock signal of said frequency synthesizer; and
enabling the disabled elements of said frequency synthesizer substantially upon detection of said transition edge.
2. The method of claim 1 wherein said elements of said frequency synthesizer comprise a phase-frequency detector and a charge pump.
3. The method of claim 1 wherein said transition edge comprises a low-to-high transition of said reference-clock signal.
4. The method of claim 1 wherein said transition edge comprises a high-to-low transition of said reference-clock signal.
5. A frequency synthesizer that includes a program/swallow counter and a prescaler, comprising:
means for disabling elements, including the program/swallow counter and not the prescaler, of said frequency synthesizer prior to starting said frequency synthesizer;
means for detecting a transition edge of a reference-clock signal of said frequency synthesizer; and
means for enabling the disabled elements of said frequency synthesizer substantially upon detection of said transition edge.
6. The frequency synthesizer of claim 5 wherein said elements of said frequency synthesizer comprise a phase-frequency detector and a charge pump.
7. The frequency synthesizer of claim 5 wherein said transition edge comprises a low-to-high transition of said reference-clock signal.
8. The frequency synthesizer of claim 5 wherein said transition edge comprises a high-to-low transition of said reference-clock signal.
9. The frequency synthesizer of claim 5 wherein said means for detecting a transition edge of a reference-clock signal comprises an edge-detection circuit.
10. The frequency synthesizer of claim 9 wherein said edge-detection circuit comprises a D-flip-flop circuit.
11. An information-processing system, comprising;
a frequency synthesizer including a phase-locked loop that includes a program/swallow counter and a prescaler; and
an edge-detect circuit for (a) disabling elements, including the program/swallow counter and not the prescaler, of said phase-locked loop prior to staffing said frequency synthesizer; (b) detecting a transition edge of a reference-clock signal of said frequency synthesizer; and (c) enabling the disabled elements of said phase-locked loop of said frequency synthesizer substantially upon detection of said transition edge.
12. The information-processing system of claim 11 wherein said elements of said phase-locked loop comprise a phase-frequency detector and a charge pump.
13. The information-processing system of claim 11 wherein said transition edge comprises a low-to-high transition of said reference-clock signal.
14. The information-processing system of claim 11 wherein said transition edge comprises a high-to-low transition of said reference-clock signal.
15. The information-processing system of claim 11 wherein said information processing system comprises a radio-frequency identification system.
16. The information-processing system of claim 11 wherein said information processing system comprises a communications system.