Half-bridge circuits employing normally on switches and methods of preventing unintended current flow therein
View Patent ↗A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.
1. A circuit comprising:
a first normally-on switch having a source, a drain and a gate, the source of the first normally-on switch electrically connected to a load and the drain of the first normally-on switch electrically connected to a supply voltage;
a second normally-on switch having a source, a drain, and a gate, the source of the second normally-on switch electrically connected to a common voltage and the drain of the second normally-on switch electrically connected to the load;
a first gate driver electrically connected between the gate and the source of the first normally-on switch;
a second gate driver electrically connected between the gate and the source of the second normally-on switch; and
a first oscillating power supply electrically connected in parallel across the drain and the source of the first normally-on switch, the first oscillating power supply configured to power the first gate driver such that, for a given voltage applied to the input to the first oscillating power supply, the first oscillating power supply generates an output voltage which is supplied to the gate of the first normally-on switch by the first gate driver;
a second oscillating power supply electrically connected in parallel across the drain and the source of the second normally-on switch, the second oscillating power supply configured to power the second gate driver such that, for a given voltage applied to the input to the second oscillating power supply, the second oscillating power supply generates an output voltage which is supplied to the gate of the second normally-on switch by the second gate driver.
2. The circuit of claim 1 , wherein the input-output characteristics of the first oscillating power supply are coordinated with the characteristics of the first normally-on switch such that the first normally-on switch is in active current limiting mode over at least 50 percent of a voltage range of 0 to the breakdown voltage of the first normally-on switch applied to the first oscillating power supply and wherein the input-output characteristics of the second oscillating power supply are coordinated with the characteristics of the second normally-on switch such that the second normally-on switch is in active current limiting mode over at least 50 percent of a voltage range of 0 to the breakdown voltage of the second normally-on switch applied to the second oscillating power supply.
3. The circuit of claim 1 , wherein the input-output characteristics of the first oscillating power supply are coordinated with the characteristics of the first normally-on switch such that the first normally-on switch is in active current limiting mode over at least 75 percent of a voltage range of 0 to the breakdown voltage of the first normally-on switch applied to the first oscillating power supply and wherein the input-output characteristics of the second oscillating power supply are coordinated with the characteristics of the second normally-on switch such that the second normally-on switch is in active current limiting mode over at least 75 percent of a voltage range of 0 to the breakdown voltage of the second normally-on switch applied to the second oscillating power supply.
4. The circuit of claim 1 , wherein the input-output characteristics of the first oscillating power supply are coordinated with the characteristics of the first normally-on switch such that the first normally-on switch does not overheat when in passive current limiting mode and wherein the input-output characteristics of the second oscillating power supply are coordinated with the characteristics of the second normally-on switch such that the second normally-on switch does not overheat when in passive current limiting mode.
5. The circuit of claim 1 , wherein the first gate driver and the second gate driver each comprise a totem pole driver.
6. The circuit of claim 1 , wherein the first normally-on switch and the second normally-on switch are JFETs.
7. The circuit of claim 1 , wherein the first oscillating power supply and the second oscillating power supply are each a self-oscillating power supply.
8. The circuit of claim 1 , wherein the first oscillating power supply and the second oscillating power supply are each non-isolated.
9. The circuit of claim 6 , wherein the first normally-on switch and the second normally-on switch are each SiC JFETs.
10. The circuit of claim 8 , wherein the first oscillating power supply and the second oscillating power supply are each Cuk converters.
11. An electrical device comprising at least one circuit as set forth in claim 1 .
12. An electrical device comprising three circuits as set forth in claim 1 arranged in parallel, wherein the device is a three-phase motor drive.
13. The circuit of claim 1 , further comprising an external controller which is adapted to bias the first normally-on switch to minimum on-resistance via the first gate driver.
14. The circuit of claim 13 , wherein the first gate driver is adapted to apply a bias voltage to the gate of the first normally-on switch (V GS ) which is equal to the output from the first oscillating power supply (−V SS ) when the external controller is not biasing the first normally-on switch to minimum on resistance.