Hot edge ring apparatus and method for increased etch rate uniformity and reduced polymer buildup
An apparatus with an edge ring configured to surround a perimeter of a semiconductor wafer in a semiconductor process, the edge ring having a plurality of protrusions located on an upper surface of the edge ring, the protrusions capable of preventing the semiconductor wafer from moving outside the bounds of a process plane. There is also an apparatus having a semiconductor process chamber and an electrostatic chuck, a semiconductor wafer, and an edge ring. There is also a method including providing a semiconductor process chamber, semiconductor wafer disposed within the semiconductor process chamber, and an edge ring, the edge ring having a plurality of protrusions located on an upper surface of the edge ring, the protrusions capable of preventing the semiconductor wafer from moving outside the bounds of a process plane. The method also includes performing an etch process on the semiconductor wafer.
1 . An apparatus, comprising:
an edge ring configured to surround a perimeter of a semiconductor wafer in a semiconductor process, the edge ring having a plurality of protrusions located on an upper surface of the edge ring, the protrusions capable of preventing the semiconductor wafer from moving outside the bounds of a process plane.
2 . The apparatus of claim 1 , wherein the edge ring includes six equally spaced protrusions.
3 . The apparatus of claim 1 , wherein the protrusions do not extend above an upper surface of the semiconductor wafer.
4 . The apparatus of claim 1 , wherein the protrusions have a height above the upper surface of the edge ring of approximately 0.035 inches.
5 . The apparatus of claim 1 , wherein the protrusions have a diameter of approximately 0.150 inches.
6 . The apparatus of claim 1 , wherein the upper surface of the edge ring is substantially planar in portions other than the protrusions.
7 . The apparatus of claim 1 , wherein the edge ring increases etch rate uniformity as compared to a standard edge ring.
8 . The apparatus of claim 1 , wherein the edge ring is made of Al 2 0 3 .
9 . The apparatus of claim 1 , wherein the edge ring reduces polymer build up as compared to a standard edge ring.
10 . An apparatus, comprising:
a semiconductor process chamber;
an electrostatic chuck disposed within the semiconductor process chamber;
a semiconductor wafer supported by the electrostatic chuck; and
an edge ring, the edge ring having a plurality of protrusions located on an upper surface of the edge ring, the protrusions capable of preventing the semiconductor wafer from moving outside the bounds of a process plane.
11 . The apparatus of claim 10 , wherein the edge ring includes six equally spaced protrusions.
12 . The apparatus of claim 10 , wherein the protrusions do not extend above an upper surface of the semiconductor wafer.
13 . The apparatus of claim 10 , wherein the protrusions have a height above the upper surface of the edge ring of approximately 0.035 inches.
14 . The apparatus of claim 10 , wherein the protrusions have a diameter of approximately 0.150 inches.
15 . The apparatus of claim 10 , wherein the upper surface of the edge ring is substantially planar in portions other than the protrusions.
16 . The apparatus of claim 10 , wherein the edge ring increases etch rate uniformity as compared to a standard edge ring.
17 . The apparatus of claim 10 , wherein the edge ring is made of Al 2 0 3 .
18 . The apparatus of claim 10 , wherein the edge ring reduces polymer build up as compared to a standard edge ring.
19 . A method, comprising:
providing a semiconductor process chamber;
providing a semiconductor wafer disposed within the semiconductor process chamber;
providing an edge ring, the edge ring having a plurality of protrusions located on an upper surface of the edge ring, the protrusions capable of preventing the semiconductor wafer from moving outside the bounds of a process plane; and
performing an etch process on the semiconductor wafer.
20 . The method of claim 19 , wherein the edge ring includes six equally spaced protrusions that do not extend above an upper surface of the semiconductor wafer.