IP Library Granted Patent US 7,598,800
Granted Patent B2
US 7,598,800 · App. 11/805,523 · Granted Oct 6, 2009

Method and circuit for an efficient and scalable constant current source for an electronic display

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Quick Facts
Patent No.
US 7,598,800
App. No.
11/805,523
Granted
Oct 6, 2009
Kind
B2
Abstract

The present invention uses two transistors instead of a sensing resistor to provide a constant current source for a load such as an array of light emitting diodes (“LEDs”). In the present invention, a bias current is applied to a branch of the circuit. The drain-to-source voltages of two transistors are matched. The voltage at the gate of both transistors is controlled based on the bias current and the drain-to-source current of the first of the two transistors. The second of the two transistors is sized such that source current of the second transistor is a multiple of the source current of the first transistor for a given gate voltage. By the techniques of this invention, the load current in a circuit is efficiently kept constant at a multiple of the input bias current.

Claims (21)

1. A constant current source circuit comprising:

a first operational amplifier having a non-inverting input, an inverting input, and an output;

a reference current source coupled to the inverting input of the first operational amplifier, wherein the reference current determines the voltage applied to the inverting input;

a first transistor having gate, drain and source terminals and having a source current that is a function of the drain-to-source voltage and the gate voltage and is independent of an additional offset current, wherein the drain terminal of the first transistor is in series with the non-inverting input of the first operational amplifier and wherein the gate terminal of the first transistor is connected to the output of the first operational amplifier;

a second transistor having gate, drain and source terminals and having a source current that is a function of the drain-to-source voltage and the gate voltage and is independent of an additional offset current, wherein the gate terminal of the second transistor is connected to the output of the first operational amplifier and wherein the source current of the second transistor is a multiple of the source current of the first transistor for a given voltage on the output of the first operational amplifier;

a third transistor having gate, drain and source terminals, wherein the drain terminal of the third transistor is connected to the non-inverting input of the first operational amplifier; and

a second operational amplifier having a non-inverting input, an inverting input, and an output, wherein the inverting input of the second operational amplifier is connected to the source terminal of the third transistor and to the drain terminal of the first transistor, and wherein the non-inverting input of the second operational amplifier is connected to the drain terminal of the second transistor.

2. The constant current source of claim 1 , wherein at least one of the transistors is a field effect transistor.

3. The constant current source of claim 1 , further comprising a light emitting diode coupled to the drain of the second transistor.

4. The constant current source of claim 1 , further comprising a light emitting diode coupled to the non-inverting input of the second operational amplifier.

5. The constant current source of claim 1 , further comprising a voltage source coupled to the inverting input of the first operational amplifier by way of a first resistor.

6. The constant current source of claim 1 , further comprising a voltage source coupled to the non-inverting input of the first operational amplifier by way of a second resistor.

7. The constant current source of claim 1 , wherein the constant current source is incorporated in a flat panel display.

8. A flat panel display including a constant current source circuit comprising:

a first operational amplifier having a non-inverting input, an inverting input, and an output;

a reference current source coupled to the inverting input of the first operational amplifier, wherein the reference current determines the voltage applied to the inverting input;

a first transistor having gate, drain and source terminals and having a source current that is a function of the drain-to-source voltage and the gate voltage and is independent of an additional offset current, wherein the drain terminal of the first transistor is in series with the non-inverting input of the first operational amplifier and wherein the gate terminal of the first transistor is connected to the output of the first operational amplifier;

a second transistor having gate, drain and source terminals and having a source current that is a function of the drain-to-source voltage and the gate voltage and is independent of an additional offset current, wherein the, gate terminal of the second transistor is connected to the output of the first operational amplifier and wherein the source current of the second transistor is a multiple of the source current of the first transistor for a given voltage on the output of the first operational amplifier;

a third transistor having gate, drain and source terminals, wherein the drain terminal of the third transistor is connected to the non-inverting input of the first operational amplifier; and

a second operational amplifier having a non-inverting input, an inverting input, and an output, wherein the inverting input of the second operational amplifier is connected to the source terminal of the third transistor and to the drain terminal of the first transistor, and wherein the non-inverting input of the second operational amplifier is connected to the drain terminal of the second transistor.

9. The flat panel display of claim 8 , wherein at least one of the transistors is a field effect transistor.

Assignments (20)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2011
From: MSILICA INCORPORATED
To: ATMEL CORPORATION
Reel/Frame 026128/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2011
From: THANDI, GURJIT S.; S, DILIP; SANTO, HENDRIK; VI, KIEN
To: MSILICA INCORPORATED
Reel/Frame 026117/0781 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2010
From: MSILICA INCORPORATED
To: ATMEL CORPORATION
Reel/Frame 025383/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2007
From: THANDI, GURJIT S.; S. DILIP; SANTO, HENDRIK; VI, KIEN
To: MSILICA
Reel/Frame 019724/0746 →