IP Library Granted Patent US 7,688,009
Granted Patent B2
US 7,688,009 · App. 11/813,985 · Granted Mar 30, 2010

LED current controller and method therefor

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Quick Facts
Patent No.
US 7,688,009
App. No.
11/813,985
Granted
Mar 30, 2010
Kind
B2
Abstract

In one embodiment, an LED current control circuit is configured with a sample and hold circuit that samples an error signal of an error amplifier during one time and holds the sampled value during a second time.

Claims (21)

1. A current controller for an LED comprising:

a switching control circuit configured to form a switching drive signal to control a current through an LED responsively to a sense signal that is representative of the current;

a first control circuit configured to receive a control signal and responsively enable the switching control circuit to form the switching drive signal, the control signal having a first state during a first time interval and a second state during a second time interval;

an error amplifier coupled to receive the sense signal and form a error signal; and

a sample and hold circuit configured to sample a value of the error signal responsively to a first portion of the first time interval that the control signal is at the first state and hold the value of the error signal responsively to a portion of the second time interval that the control signal is at the second state to form a held value of the error signal, the sample and hold circuit configured to couple the held value to the switching control circuit responsively to a second portion of the first time interval that the control signal is at the first state and couple the error signal to the switching control circuit after the second portion of the first time interval.

2. The current controller of claim 1 wherein the sample and hold circuit is configured to sample the value of the error signal responsively to the first time interval after the control signal transitions to the first state.

3. The current controller of claim 2 wherein the sample and hold circuit includes a delay element that forms the second portion of the first time interval.

4. The current controller of claim 1 wherein the sample and hold circuit is configured to hold the value of the error signal responsively to the second time interval after the control signal transitions to the second state.

5. The current controller of claim 4 further including a first transistor having a first current carrying electrode coupled to receive the error signal, a second current carrying electrode coupled to charge a capacitor, and a control electrode; a second transistor having a first current carrying electrode coupled to receive a signal from the capacitor, a second current carrying electrode, and a control electrode coupled to the control electrode of the first transistor and operably coupled to enable the first and second transistors responsively to the first time interval after the control signal transitions to the first state; and a third transistor having a first current carrying electrode coupled to the second current carrying electrode of the first transistor, a second current carrying electrode coupled to the second current carrying electrode of the second transistor, and a control electrode operably coupled to enable the third transistor responsively to the second time interval after the control signal transitions to the second state.

6. The current controller of claim 1 wherein the sample and hold circuit is configured to couple the held value of the error signal to the switching control circuit until the second portion of the first time interval and to couple the error signal to the switching control circuit after the first portion of the first time interval.

7. The current controller of claim 6 further including a timing circuit coupled to form the second portion of the first time interval responsively to the control signal transition to the first state.

8. The current controller of claim 7 wherein the sample and hold circuit includes a latch configured to be set responsively to the second state of the control signal and to be reset responsively to the second portion of the first time interval.

9. The current controller of claim 8 wherein a delay element is coupled to form the second portion of the first time interval.

10. The current controller of claim 8 further including a first transistor having a first current carrying electrode coupled to receive the error signal, a second current carrying electrode, and a control electrode operably coupled to enable the first transistor after the second portion of the first time interval, and a second transistor having a first current carrying electrode coupled to receive the held value of the error signal, a second current carrying electrode coupled to the second current carrying electrode of the first transistor and to the switching control circuit, and a control electrode operably coupled to enable the second transistor during the second portion of the first time interval.

11. A method of forming a current controller comprising:

coupling a control circuit to control a sample and hold circuit;

configuring the control circuit to receive a control signal and responsively control the sample and hold circuit to sample an input signal that is received on an input of the sample and hold circuit responsively to a portion of a first state of the control signal, to hold a sampled value of the input signal responsively to a second state of the control signal to form a held value, and to couple the held value to an output of the sample and hold circuit for a first time period after the control signal transitions to the first state.

12. The method of claim 11 wherein configuring the control circuit to receive the control signal and responsively control the sample and hold circuit includes configuring the control circuit to form the first time period with a length that is greater than a time required for the input signal on the input to become stable.

13. The method of claim 11 wherein configuring the control circuit to receive the control signal and responsively control the sample and hold circuit includes configuring the control circuit to form the first time period to be approximately three microseconds.

14. The method of claim 11 wherein configuring the control circuit to receive the control signal and responsively control the sample and hold circuit includes configuring the control circuit to couple the output of the sample and hold circuit to a PWM circuit.

15. The method of claim 11 wherein configuring the control circuit to receive the control signal and responsively control the sample and hold circuit includes configuring the current controller to begin a control cycle responsively to the first state of the control signal.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →