IP Library Granted Patent US 7,843,181
Granted Patent B2
US 7,843,181 · App. 11/817,766 · Granted Nov 30, 2010

DC-DC converter controller having optimized load transient response and method

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Quick Facts
Patent No.
US 7,843,181
App. No.
11/817,766
Granted
Nov 30, 2010
Kind
B2
Abstract

A power supply controller ( 25 ) is configured to accurately adjust the value of an output voltage of a power supply system ( 10 ) responsively to the output voltage increasing to an undesirable value. The controller ( 25 ) accurately limits an upper value of the output voltage during a light load condition, and rapidly reduces the value of the output voltage to a desired value. The power supply controller is configured to turn off the first output transistor but inhibit turning off the second output transistor using two different control signals.

Claims (21)

1. A method of forming a power supply controller comprising:

configuring the power supply controller to form a drive signal having switching cycles that are used to control a first switch and a second switch to regulate an output voltage to a first value wherein a cycle includes enabling and disabling the first switch during each switching cycle and also includes enabling the second switch during each switching cycle;

configuring a first control circuit of the power supply controller to set a first state of a first control signal responsively to a second value of the output voltage that is greater than the first value and responsively inhibit subsequent switching cycles of the power supply controller; and

configuring a second control circuit to turn the first switch off and not turn the second switch off responsively to inhibiting the subsequent switching cycles during at least a portion of time that the subsequent switching cycles are inhibited.

2. The method of claim 1 further including configuring the second control circuit to force the second switch to conduct a first current during the portion of time.

3. The method of claim 2 wherein configuring the second control circuit to force the second switch to conduct the first current includes selectively coupling the second switch in a first current mirror configuration to receive a control signal having a value that is ratioed to a current of a current source.

4. The method of claim 3 wherein selectively coupling the second switch in the first current mirror configuration includes coupling a second current mirror to form a second current that is ratioed to the current of the current source.

5. The method of claim 1 wherein configuring the second control circuit includes configuring the second control circuit to control a Vgs of the second switch to be no less than a threshold voltage of the second switch.

6. The method of claim 1 further including coupling a first transistor as the first switch, and selectively coupling a second transistor as the second switch in a first current mirror configuration with a third transistor to control a first current through the second switch.

7. The method of claim 6 wherein selectively coupling the second transistor includes selectively coupling the second transistor in the first current mirror configuration responsively to a control signal received from the first control circuit.

8. A method of forming a power supply controller comprising:

configuring the power supply controller to control a first switch and a second switch to regulate an output voltage to a first value, the first switch including a first transistor;

configuring a first control circuit of the power supply controller to set a first state of a first control signal responsively to a second value of the output voltage that is greater than the first value and responsively inhibit subsequent switching cycles of the power supply controller; and

configuring a second control circuit to turn the first switch off and not turn the second switch off during at least a portion of time that the subsequent switching cycles are inhibited; and

selectively coupling a second transistor as the second switch in a first current mirror configuration with a third transistor to control a first current through the second switch and selectively coupling the first current mirror to receive a second current and force the first current to be a ratio of the second current.

9. A method of forming a power supply controller comprising:

configuring the power supply controller to control a first switch and a second switch to regulate an output voltage to a first value, the first switch including a first transistor;

configuring a first control circuit of the power supply controller to set a first state of a first control signal responsively to a second value of the output voltage that is greater than the first value and responsively inhibit subsequent switching cycles of the power supply controller; and

configuring a second control circuit to turn the first switch off and not turn the second switch off during at least a portion of time that the subsequent switching cycles are inhibited; and

selectively coupling a second transistor as the second switch in a first current mirror configuration with a third transistor to control a first current through the second switch including coupling a fourth transistor to selectively couple a control electrode of the third transistor to a first current carrying electrode of the third transistor, to a control electrode of the second transistor and to receive a second current from a second current mirror.

10. The method of claim 9 further including configuring the second current mirror to from the second current as a ratio of a third current of a current source.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →