Fast AC coupled level translator
View Patent ↗A level translator has a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary. A pair of capacitors are provided, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN and to a gate of a first transistor of the pair of complimentary transistors and a second capacitor of the pair of capacitors is coupled the voltage input VIN and to a gate of a second transistor of the pair of complimentary transistors. A flip flop device is provided having a first input coupled to a drain of the first transistor, and a second input coupled to a drain of the second transistor. A pair of resistors is provided, wherein a first resistor of the pair of resistors is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second resistor of the pair of resistors is coupled to the gate of the second transistor and to a voltage supply VSS. A pair of clamping circuits is provided, wherein a first clamping circuit of the pair of clamping circuits is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second clamping circuit of the pair of clamping circuits is coupled to the gate of the second transistor and to a voltage supply VSS.
1. A level translator comprising:
a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary;
a pair of capacitors, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN and to a gate of a first transistor of the pair of complimentary transistors and a second capacitor of the pair of capacitors coupled the voltage input VIN and to a gate of a second transistor of the pair of complimentary transistors;
a flip flop device having a first input coupled to a drain of the first transistor, and a second input coupled to a drain of the second transistor,
a pair of resistors, wherein a first resistor of the pair of resistors is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second resistor of the pair of resistors is coupled to the gate of the second transistor and to a voltage supply VSS; and
a pair of clamping circuits, wherein a first clamping circuit of the pair of clamping circuits is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second clamping circuit of the pair of clamping circuits is coupled to the gate of the second transistor and to a voltage supply VSS;
wherein a source of the first transistor is connected to a first pole of a power source, a source of the second transistor is connected to a second pole of the power source, a drain of the first transistor is connected to a first input of the flip-flop, a drain of the second transistor is connected to a second input of the flip-flop, a gate of the first transistor being further connected to the first clamp circuit, and a gate of the second transistor being further connected to the second clamp circuit;
wherein an additional at least one of a reset or set input is provided on the flip-flop for determining the state of the flip-flop at an arbitrary time; and
wherein a voltage change detector is coupled to the flip flop to control at least one of a reset or set input of the flip-flop.
2. A level translator in accordance with claim 1 wherein the pair of complimentary transistors comprises a pair of complimentary MOS transistors.
3. A level translator in accordance with claim 1 , wherein the flip-flop is made with two CMOS inverters connected in opposition to form a memory circuit with two stable states.
4. A level translator in accordance with claim 1 , wherein at least one output of the flip-flop is connected to an input of at least one of a logic gate or an inverter.
5. A complementary MOS field effect transistor amplifier for AC input signals, comprising:
a voltage detection circuit comprising:
a first transistor having a first predetermined voltage threshold; and
a second transistor having a second predetermined voltage threshold, the first and second transistors having control gates and being of complementary conductivity;
a first coupling capacitor coupled to the gate of the first transistor;
a second coupling capacitor coupled to the gate of the second transistor;
a first resistor coupled to the gate of the first transistor and to a source of the first transistor;
a second resistor coupled to the gate of the second transistor and to a source of the second transistor;
a first clamp circuit coupled to the gate of the first transistor for limiting a gate voltage of the first transistor; and
a second clamp circuit coupled to the gate of the second transistor for limiting a gate voltage of the second transistor;
wherein the source of the first transistor is connected to a first pole of a power source, the source of the second transistor is connected to a second pole of the power source, the drain of the first transistor is connected to a first input of a flip-flop, the drain of the second transistor is connected to a second input of the flip-flop, the gate of the first transistor being further connected to the first clamp circuit, and the gate of the second transistor being further connected to the second clamp circuit;
wherein an additional at least one of a reset or set input is provided on the flip-flop for determining the state of the flip-flop at an arbitrary time; and
wherein a voltage change detector is coupled to the flip flop to control at least one of a reset or set input of the flip-flop.
6. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein the first and second inputs of the flip-flop are connected to a same node, the flip-flop state being determined by whether current is forced into or out of the same node.
7. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 6 , wherein the flip-flop comprises a pair of CMOS inverters connected in opposition to form a memory circuit with two stable states.
8. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein at least one output of the flip-flop is connected to an input of at least one of a logic gate or an inverter.
9. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein output voltages of the first and second clamp circuits are chosen to minimize current consumption of the amplifier for a given load.
10. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein at least one of the first and second clamp circuits contains a MOS transistor.
11. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein the first and second capacitors are driven by the same signal source.
12. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 5 , wherein at least one of the resistors is made with an MOS transistor.
13. A complementary MOS field effect transistor amplifier for AC input signals, comprising:
a voltage detection circuit comprising:
a first transistor having a first predetermined voltage threshold; and
a second transistor having a second predetermined voltage threshold, the first and second transistors having control gates and being of complementary conductivity;
a first coupling capacitor coupled to the gate of the first transistor;
a second coupling capacitor coupled to the gate of the second transistor;
a first resistor coupled to the gate of the first transistor and to a source of the first transistor;
a second resistor coupled to the gate of the second transistor and to a source of the second transistor;
a first clamp circuit coupled to the gate of the first transistor for limiting a gate voltage of the first transistor; and
a second clamp circuit coupled to the gate of the second transistor for limiting a gate voltage of the second transistor;
wherein the source of the first transistor is connected to a first pole of a power source, the source of the second transistor; is connected to a second pole of the power source, the drain of the first transistor is connected to a first input of a flip-flop, the drain of the second transistor is connected to a second input of the flip-flop, the gate of the first transistor being further connected to the first clamp circuit, and the gate of the second transistor being further connected to the second clamp circuit;
wherein an additional at least one of a reset or set input is provided on the flip-flop for determining the state of the flip-flop at an arbitrary time; and
wherein a DC coupled level translator is used to control at least one of a reset or set input of the flip-flop.
14. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 13 , wherein the first and second inputs of the flip-flop are connected to a same node, the flip-flop state being determined by whether current is forced into or out of the same node.
15. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 14 , wherein output voltages of the first and second clamp circuits are chosen to minimize current consumption of the amplifier for a given load.
16. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 14 , wherein an additional at least one of a reset or set input is provided on the flip-flop for determining the state of the flip-flop at an arbitrary time.
17. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 13 , wherein the flip-flop comprises a pair of CMOS inverters connected in opposition to form a memory circuit with two stable states.
18. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 14 , wherein at least one output of the flip-flop is connected to an input of at least one of a logic gate or an inverter.
19. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 13 , wherein a logic state comparator is used to determine a correspondence of an output of the DC coupled level translator to the output of the amplifier.
20. A complementary MOS field effect transistor amplifier for AC input signals in accordance with claim 19 , wherein a timer is used to determine when the output of the logic state comparator is used.