Low noise, low power, high linearity differential amplifier with a capacitive input impedance
View Patent ↗A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.
1. A low noise, low power differential two-stage amplifier comprising:
an electrical element;
exactly one pair of input devices adapted to supply a capacitive load to said electrical element requiring said capacitive load, wherein said pair of input devices are adapted to act as a voltage source follower;
a first resistive element operatively connected to said pair of input devices and adapted to receive said capacitive load from said pair of input devices;
a second resistive element adapted to receive current from said first resistive element;
a third resistive element adapted to receive current from said first resistive element, wherein the second and third resistive elements are sized differently than said first resistive element in order to provide a voltage gain;
a feedback loop operatively connected to said electrical element and the resistive elements; and
a gain transistor adapted to sense and increase a loop gain of said feedback loop while said feedback loop is closed.
2. The amplifier of claim 1 , wherein said gain transistor comprises a Class A output stage.
3. The amplifier of claim 1 , wherein said gain transistor comprises a Class AB output stage.
4. The amplifier of claim 1 , further comprising a compensation network comprising a capacitor.
5. The amplifier of claim 4 , further comprising a resistor in series with said capacitor.
6. The amplifier of claim 4 , further comprising a transistor in series with said capacitor.
7. The amplifier of claim 1 , wherein the devices adapted to provide a capacitive load comprises any of a pair of transistors, a pair of resistors, a resistor degenerated metal oxide semiconductor (MOS) device, and a dual NMOS and PMOS device.
8. The amplifier of claim 1 , wherein said feedback loop comprises a common mode load feedback circuit operatively connected to at least one of the input devices.
9. A low noise, low power differential amplifier comprising:
a first stage comprising a pair of electrical devices that sense an input signal difference across said pair of electrical devices; and
a control feedback loop operatively connected to said first stage, wherein said first stage in combination with said control loop feedback is adapted to place an exact copy of said signal across a first pair of resistive components, wherein said first pair of resistive components are adapted to generate a differential signal current, wherein said control feedback loop is adapted to ensure that said differential signal current goes to a second pair of resistive components to generate a voltage output, and wherein said control loop feedback comprises a common mode loop.
10. The amplifier of claim 9 , wherein the first and second pair of resistive components are in ratio to produce said exact copy of said signal with some gain at an output of said first stage.
11. The amplifier of claim 9 , further comprising at least one additional stage operatively connected to said first stage.
12. A method of reducing noise and power in a differential two-stage amplifier, said method comprising:
inputting a signal;
supplying a capacitive load to an electrical element requiring said capacitive load using exactly one pair of input devices, wherein said pair of input devices are adapted to act as a voltage source follower;
transmitting said capacitive load from said pair of input devices to a first resistive element operatively connected to said pair of input devices;
transmitting current from said first resistive element to each of a second resistive element and a third resistive element, wherein the second and third resistive elements are sized greater than said first resistive element in order to provide a voltage gain; and
using a control feedback loop to place an exact copy of said signal across said first resistive element, wherein said first resistive element is adapted to generate a differential signal current, wherein said control feedback loop is adapted to ensure that said differential signal current goes to said second resistive element to generate a voltage output.
13. The method of claim 12 , further comprising using a gain transistor to sense and increase a loop gain of said control feedback loop while said control feedback loop is closed.
14. The method of claim 13 , wherein said gain transistor comprises a Class A output stage.
15. The method of claim 13 , wherein said gain transistor comprises a Class AB output stage.
16. The method of claim 12 , further comprising configuring a compensation network comprising a capacitor in the amplifier.
17. The method of claim 16 , further comprising configuring a resistor in series with said capacitor.
18. The method of claim 16 , further comprising configuring a transistor in series with said capacitor.
19. The method of claim 12 , wherein the devices adapted to provide a capacitive load comprises any of a pair of transistors, a pair of resistors, a resistor degenerated metal oxide semiconductor (MOS) device, and a dual NMOS and PMOS device.
20. The method of claim 12 , wherein said control loop feedback comprises a common mode loop.