IP Library › Granted Patent US 7,549,138
Granted Patent B2
US 7,549,138 · App. 11/837,700 · Granted Jun 16, 2009

Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,549,138
App. No.
11/837,700
Granted
Jun 16, 2009
Kind
B2
Abstract

The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

Claims (27)

1. In a FPGA having a plurality of individually programmable tiles of logic modules, each logic module including a plurality of antifuses, a method for programming selected antifuses in each of the tiles comprising:

loading for each tile address data identifying ones of the plurality of antifuses designated for programming;

selecting for each tile the address of one of the antifuses designated for programming;

programming concurrently in each tile the antifuse identified by the selected address;

determining whether all of the selected antifuses designated for programming have been programmed;

continuing to program any ones of the antifuses designated for programming that have not been programmed;

soaking the programmed antifuses in each tile;

determining whether the antifuse designated for programming in each tile has been programmed;

determining whether all antifuses designated for programming have been programmed; and

repeating the selecting, programming, determining and the soaking if all antifuses designated for programming have not been programmed.

2. The method of claim 1 wherein loading for each tile address data identifying ones of the plurality of antifuses designated for programming comprises setting a mask bit for the designated antifuse.

3. The method of claim 1 further including resetting the mask register bit in each tile for each antifuse that has been programmed.

4. The method of claim 3 wherein soaking the programmed antifuses in each tile and resetting the mask register bit in each tile are performed simultaneously.

5. The method of claim 1 wherein loading for each tile address data identifying ones of the plurality of antifuses designated for programming further comprises identifying the address data from a netlist describing the circuit to be programmed into the FPGA.

6. The method of claim 1 wherein selecting for each tile the address of one of the antifuses designated for programming comprises selecting the address of one of the antifuses associated with a mask register bit that has been set.

7. The method of claim 1 wherein determining whether all antifuses designated for programming have been programmed comprises determining whether any mask register bits remain set.

8. In a FPGA having a plurality of individually programmable tiles of logic modules, each logic module including a plurality of antifuses, apparatus for programming selected antifuses in each of the tiles comprising:

means for loading for each tile address data identifying ones of the plurality of antifuses designated for programming;

means for selecting for each tile the address of one of the antifuses designated for programming;

means for programming concurrently in each tile the antifuse identified by the selected address;

means for determining whether all of the selected antifuses designated for programming have been programmed;

means for continuing to program any ones of the antifuses designated for programming that have not been programmed;

means for soaking the programmed antifuses in each tile;

means for determining whether the antifuse designated for programming in each tile has been programmed;

means for determining whether all antifuses designated for programming have been programmed; and

means for repeating the selecting, programming, determining and the soaking if all antifuses designated for programming have not been programmed.

9. The apparatus of claim 7 wherein means for loading for each tile address data identifying ones of the plurality of antifuses designated for programming further comprises means for identifying the address data from a netlist describing the circuit to be programmed into the FPGA.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
CHANGE OF NAME Recorded Dec 28, 2015
From: ACTEL CORPORATION
To: MICROSEMI SOC CORP.
Reel/Frame 037393/0562 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →