Apparatus and method for initializing an integrated circuit device and activating a function of the device once an input power supply has reached a threshold voltage
View Patent ↗An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.
1. An apparatus configured to generate a power-on-reset using a power-on-reset signal line, said apparatus comprising:
a power-on-reset circuit having an input and an output;
an oscillator circuit having an input and an output, said input coupled to said output of said power-on-reset circuit;
at least one memory test device having a data input, an output, a set input, a reset input, a row-control signal line, and a column-control signal line, one of said set input and said reset input of each said at least one memory test device coupled to said output of said power-on-reset circuit, said row-control signal line and said column-control signal line coupled to said output of said oscillator circuit; and
a buffer having an input and an output, said input coupled to said output of said memory test device and said output coupled to said power-on-reset signal line.
2. The apparatus of claim 1 wherein said data input is coupled to a VDD power line when said reset input is coupled to said output of said power-on-reset circuit.
3. The apparatus of claim 1 wherein said data input is coupled to ground when said set input is coupled to said output of said power-on-reset circuit.
4. The apparatus of claim 1 wherein said oscillator is coupled to said row-control signal line and a column-control signal line of said memory test device through a frequency divider.
5. The apparatus of claim 1 wherein said memory test device further comprises a memory cell coupled to a data input line through a bit-line driver, a bit-line and a plurality of pass-transistors.
6. The apparatus of claim 5 wherein said bit-line is coupled to a resistor and a capacitor.
7. An apparatus configured to generate a power-on-reset memory signal through a power-on-reset memory signal line and a clock signal through said power-on-reset memory signal output line, said apparatus comprising:
a power-on-reset circuit having an input and an output;
an oscillator circuit having an input and an output, said input coupled to said output of said power-on-reset circuit;
at least one memory test device having a data input, an output, a set input, a reset input, a row-control signal line, and a column-control signal line, one of said set input and said reset input of each said at least one memory test device coupled to said output of said power-on-reset circuit, said row-control signal line and said column-control signal line coupled to said output of said oscillator circuit; and
a buffer having an input and an output, said input coupled to said output of said memory test device and said output coupled to said power-on-reset memory signal line.
8. The apparatus of claim 3 wherein said data input is coupled to a VDD power line when said reset input is coupled to said output of said power-on-reset circuit.
9. The apparatus of claim 3 wherein said data input is coupled to ground when said set input is coupled to said output of said power-on-reset circuit.
10. The apparatus of claim 3 further comprising a two-input combinatorial circuit having a first input, a second input, and an output, said first input coupled to said output of said oscillator circuit, said second input coupled to said output of said buffer, and said output coupled to a clock memory signal line.
11. The apparatus of claim 3 wherein said oscillator is coupled to said row-control signal line and a column-control signal line of said memory test device through a frequency divider.
12. The apparatus of claim 3 wherein said memory test device further comprises a memory cell coupled to a data input line through a bit-line driver, a bit-line and a plurality of pass-transistors.
13. The apparatus of claim 12 wherein said bit-line is coupled to a resistor and a capacitor.
14. The apparatus of claim 10 wherein said output of said buffer is coupled to said second input of said two-input combinatorial circuit through a delay element.
15. An apparatus configured to generate a power-on-reset and a clock signal comprising:
a power-on-reset circuit having an output coupled to a first input of a three-input combinatorial circuit;
an oscillator circuit having an input and an output, said input coupled to said output of said power-on-reset circuit, said output coupled to a plurality of frequency dividers having a first output carrying a first clock signal, and said second output carrying a second clock signal;
a first memory test device having a data input, a rest input, a row-control signal, a column-control signal, and an output, said data input coupled to VDD, said reset input coupled to said output of said a power-on-reset circuit, said row-control signal line and said column-control signal line coupled to said second output of said plurality of frequency dividers, and said output coupled to a second input of said three-input combinatorial circuit;
a second memory test device having a data input, a preset input, a row-control signal line, a column-control signal line, and an output, said data input coupled to ground, said preset input coupled to said output of said a power-on-reset circuit, said row-control signal line and said column-control signal line coupled to said second output of said plurality of frequency dividers, and said output coupled to a third input of said three-input combinatorial circuit;
a power-on-reset memory signal line coupled to an output of said three-input combinatorial circuit and configured to carry said power-on-reset memory signal;
a latch having first input, a second input, a third input, and an output, said first input coupled to said output of power-on-reset circuit, said second input coupled to said output of said second output of said frequency divider, and said third input coupled to said output of said three-input combinatorial circuit; and
a two-input combinatorial circuit having a first input, a second input, and an output, said first input coupled to said first output carrying a first clock signal of said plurality of frequency dividers, said second input coupled to said output of said latch, and said output coupled to said clock memory signal line.
16. The apparatus of claim 15 wherein said memory test device further comprises a memory cell coupled to a data input line through a bit-line driver, a bit-line and a plurality of pass-transistors.
17. The apparatus of claim 16 wherein said bit-line is coupled to a resistor and a capacitor.
18. A method of generating a power-on-reset clock signal immediately after power up comprising:
coupling an input of an oscillator circuit to an output of a power-on-reset circuit;
coupling a reset input of a memory test device to said output of said power-on-reset circuit, wherein said data input of said memory test device is coupled to a VDD power line,
coupling a row-control signal line and a column-control signal line of said memory test device to an output of said oscillator circuit;
coupling a buffer having an input to an output of said memory test device; and
coupling an output of said buffer to a power-on-reset signal line.
19. The method of claim 18 further comprising:
coupling said oscillator to said row-control signal line and said column-control signal line of said memory test device through a frequency divider.
20. The method of claim 18 wherein said memory testing device further comprises a memory cell coupled to a data input line through a bit-line driver, a bit-line and a plurality of pass-transistors.
21. The method of claim 20 wherein said bit-line is coupled to a resistor and a capacitor.