Apparatus and method for initializing an integrated circuit device and activating a function of the device once an input power supply has reached a threshold voltage
View Patent ↗An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating a test activation signal, a test circuit receiving the test activation signal and generating a test result signal, and a threshold decision circuit receiving the test result signal and generating the function activation signal. The test circuit models a function of the integrated circuit device and generates the test result signal when the power input has reached a sufficient voltage to perform the function of the integrated circuit device. The threshold decision circuit generates the function activation signal if the test result signal indicates the power input has reached a sufficient voltage to perform the function of the integrated circuit device.
1. A method of generating a power-on-reset clock signal immediately after power up comprising:
coupling a power-on-reset output from a power-on-reset circuit to an input of an oscillator circuit to produce a first clock signal and to a reset input of a latch;
coupling a reset input of a memory test device to said output of said power-on-reset circuit, wherein said data input of said memory test device is coupled to a VDD power line;
coupling a row-control signal line and a column-control signal line of said memory test device to an output of said oscillator circuit;
coupling an output of said oscillator circuit to a first frequency divider;
coupling an output of said first frequency divider to an input of a second frequency divider;
coupling an output of said second frequency divider to an Nth frequency divider, wherein said first clock signal reaches a desired frequency for clearing and programming operations;
coupling to the output of said oscillator circuit to a first input of a two-input combinational circuit;
coupling an output of said Nth frequency divider to a second input of a two-input combinatorial circuit through said latch, wherein an output of said two-input combinatorial circuit generates a second clock signal through a clock signal output line.
2. The method of claim 1 wherein said memory testing device further comprises a memory cell coupled to a data input line through a bit-line driver, a bit-line and a plurality of pass-transistors.
3. The method of claim 2 wherein said bit-line is coupled to a resistor and a capacitor.