Integrated circuit for a data transmission system and receiving device of a data transmission system
View Patent ↗The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface, and c) a test unit for testing the functionality of the functional units, whereby the test unit has at least two operating modes and at least one gate terminal for switching between the operating modes and is designed to connect circuit points, assigned to a specific operating mode, of the functional units to terminals of the integrated circuit, when the test unit is operated in the specific operating mode. According to the invention, the at least one gate terminal of the test unit is connected to the TAP controller and the integrated circuit is designed to switch between the operating modes depending on the internal states of the TAP controller. The invention relates furthermore to a receiving device of a data transmission system.
1. An integrated circuit for a data transmission system, the integrated circuit comprising
a plurality of functional units;
a TAP controller having a JTAG interface; and
a test unit for testing a functionality of the functional units, the test unit having at least two operating test modes and at least one gate terminal for switching between operating test modes and is designed to connect circuit points assigned to a specific operating mode of the functional units to terminals of the integrated circuit when the test unit is operated in a specific operating test mode,
wherein the at least one gate terminal of the test unit is connected to the TAP controller, and
wherein the integrated circuit is designed to switch between the operating test modes depending on an internal states of the TAP controller.
2. The circuit according to claim 1 , wherein the integrated circuit is designed to switch between the operating test modes when the TAP controller assumes at least two predefinable internal states.
3. The circuit according to claim 1 , wherein the integrated circuit has an additional JTAG interface connected to the JTAG interface of the TAP controller for applying and picking up JTAG signals and is designed to operate the test unit in a specific operating test mode when JTAG signals assigned to the specific operating test mode are applied at the additional JTAG interface.
4. The circuit according to claim 1 , wherein the test unit has a multiplexer connected to the functional units and the terminals of the integrated circuit for controllable connection of the specific circuit points of the functional units to the terminals.
5. The circuit according to claim 4 , further comprising a control unit connected to the multiplexer and the TAP controller for driving the multiplexer depending on the internal states of the TAP controller.
6. The circuit according to claim 5 , wherein the control unit is designed to receive the internal states of the TAP controller, to load and save a bit sequence assigned to a desired operating test mode, and to control the multiplexer with the stored bit sequence.
7. The circuit according to claim 6 , wherein the control unit is designed to load the bit sequence when one of two predefinable states is received.
8. The circuit according to claim 7 , wherein the TAP controller has a state machine with a number of internal states.
9. The circuit according to claim 5 , wherein the control unit has a mode register, connected to the multiplexer, for storing a bit sequence assigned to a desired operating test mode.
10. The circuit according to claim 9 , wherein the control unit has a shift register connected to the mode register for loading the bit sequence.
11. The circuit according to any claim 5 , wherein the control unit has a decoder connected to the TAP controller for receiving the internal states of the TAP controller.
12. The circuit according to claim 1 , wherein the integrated circuit has a microcontroller for controlling the functional units.
13. The circuit according to claim 12 , wherein the microcontroller comprises the TAP controller.
14. The circuit according to claim 1 , wherein at least one functional unit is designed as a memory unit, interface unit, a voltage monitoring unit, a decoder, an arbiter, or as an analogous unit.
15. A receiving device for a data transmission system comprising at least one integrated circuit according to claim 1 .
16. The receiving device according to claim 15 wherein the receiving device is designed for satellite-supported position sensing.
17. The circuit according to claim 1 , wherein the TAP controller functions according to IEEE 1149.