FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation
View Patent ↗An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
1. An interconnect architecture for a programmable logic device comprising:
a plurality of interconnect routing lines;
a plurality of first-level multiplexers each having data inputs and a data output, the data inputs of the first-level multiplexers connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer;
a plurality of second-level multiplexers each having data inputs and a data output, the second-level multiplexers organized into multiplexer groups;
a plurality of lookup tables, each lookup table associated with one of the multiplexer groups and having a plurality of lookup table inputs, each lookup table input coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated;
wherein the data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
2. An interconnect architecture for a programmable logic device comprising:
a plurality of interconnect routing lines;
a plurality of first-level multiplexers each having data inputs and a data output, the data inputs of the first-level multiplexers connected to the plurality of interconnect routing lines;
a plurality of second-level multiplexers each having data inputs and a data output, the second-level multiplexers organized into multiplexer groups;
a plurality of lookup tables, each lookup table associated with one of the multiplexer groups and having a plurality of lookup table inputs, each lookup table input coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated;
wherein the number of first-level multiplexers is equal to at least the number of second-level multiplexers.
3. An interconnect architecture for a programmable logic device comprising:
a plurality of interconnect lines;
a plurality of first-level multiplexers, each having a plurality of inputs and an output;
a plurality of second-level multiplexers, each having a plurality of inputs and an output;
a plurality of look up tables, each having a plurality of inputs; and
wherein the plurality of first-level multiplexers is organized into groups, the plurality of second-level multiplexers is organized into groups, each group corresponding to a look up table, each input of each look up table is connected to the output of a second-level multiplexer, a first input of a first multiplexer in each group of second-level multiplexers is connected to the output of a first multiplexer in a first group of first-level multiplexers, and each input of each first level multiplexer is connected to an interconnect line.