Method of forming low capacitance ESD device and structure therefor
View Patent ↗In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
1. An electro static discharge (ESD) device comprising:
a first terminal of the ESD device;
a second terminal of the ESD device;
a zener diode having an anode coupled to the second terminal of the ESD device and also having a cathode;
a first P-N diode coupled in series with the zener diode, the first P-N diode having an anode and a cathode; and
a second P-N diode coupled in parallel with series combination of the zener diode and the first P-N diode, the second P-N diode having a cathode and also having an anode that is coupled to the anode of the zener diode and 15 to the second terminal of the ESD device;
wherein the ESD device comprises:
a semiconductor substrate of a first conductivity type having a first peak doping concentration no less than approximately IX1019 atoms/cm3;
a first semiconductor region of a second conductivity type having approximately the first peak doping concentration and forming a first P-N junction with the semiconductor substrate wherein the first P-N junction forms a junction of the zener diode;
a second semiconductor region of the second conductivity type on the first semiconductor region and also on a portion of the semiconductor substrate wherein the second semiconductor region has a second peak doping concentration that is less than the first peak doping concentration;
a first doped region of the first conductivity type positioned in the second semiconductor region and overlying the first semiconductor region, the first doped region spaced a distance of at least two microns from the first semiconductor region, the first doped region having approximately the first peak doping concentration; and
a first trench isolation region extending from a top surface of the second semiconductor region, through the first semiconductor region, and into the semiconductor substrate wherein the first trench isolation region surrounds an outside perimeter of the first doped region.
2. The ESD device of claim 1 wherein the anode of the first P-N diode is coupled to the cathode of the second P-N diode and to the first terminal of the ESD device and wherein the cathode of the zener diode is coupled to the cathode of the first P-N diode.
3. The ESD device of claim 1 further including a second zener diode having a cathode that is coupled to the cathode of the second P-N diode and having an anode that is coupled to the first terminal of the ESD device.
4. The ESD device of claim 1 wherein the second semiconductor region is devoid of a doped region of the first conductivity type positioned between the first semiconductor region and the first doped region.
5. The ESD device of claim 1 wherein the second peak 25 doping concentration is no greater than approximately IX10 17 atoms/cm3 and wherein the first P-N diode and the second P-N diode have a zero bias capacitance of less than approximately one pico-farad.
6. The ESO device of claim 1 further including a second doped region of the second conductivity type positioned in the second semiconductor region and not overlying the first semiconductor region, the second doped region spaced a second distance from the first doped region and also positioned outside of the first trench isolation region and spaced a distance of at least two microns from the first semiconductor region, the second doped region having approximately the first peak doping concentration; and
a second trench isolation region extending from the top surface of the second semiconductor region, through the second semiconductor region, and into the semiconductor substrate wherein the second trench isolation region surrounds an outside perimeter of the second doped region.
7. The ESD device of claim 1 wherein current flow through the ESD device is vertical through the semiconductor substrate to a conductor on a surface of the semiconductor substrate that is opposite to the second semiconductor region.