Stress relief structures for silicon interposers

1. A structure, comprising:

a carrier;

a silicon interposer mechanically connected to a top surface of said carrier, said interposer having vias extending from a top surface of said interposer, through said interposer, to a bottom surface of said interposer, said vias that are exposed at said bottom surface of said interposer electrically connected to wires exposed in a top surface of said carrier;

an integrated circuit chip mechanically connected to said top surface of said interposer, electrically conductive pads exposed at a surface of said integrated circuit chip electrically connected to said vias exposed in said top surface of said interposer;

one or more stress relief structures formed entirely in said interposer, said one or more stress relief structures either (i) not electrically connected to said vias of said interposer or to said electrically conductive pads of said integrated circuit chip or (ii) electrically connected to ground through said vias of said interposer or through said electrically conductive pads of said integrated circuit chip; and

wherein said one or more stress relief structures are in tensile stress.

2. The structure of claim 1 , wherein said one or more stress relief structures are attached to said interposer by solder.

3. The structure of claim 1 , wherein said one or more stress relief structures are attached to said interposer by adhesive.

4. The structure of claim 1 , wherein said one or more stress relief structures extend between said integrated circuit chip and said interposer.

5. The structure of claim 1 , wherein said one or more stress relief structures are positioned on regions of said interposer that are adjacent to a perimeter of said integrated circuit chip.

6. The structure of claim 1 , wherein said one or more stress relief structures comprise a material selected from the group consisting of silicon, tungsten, ceramic, silicon dioxide, silicon nitride, tantalum, titanium, tantalum nitride, titanium nitride and Invar.

7. The structure of claim 1 , wherein said interposer is physically and electrically attached to said carrier by solder balls.

8. A method, comprising:

connecting a silicon interposer to a top surface of a carrier, said interposer having vias extending from a top surface of said interposer, through said interposer, to a bottom surface of said interposer, said vias that are exposed at said bottom surface of said interposer electrically connected to wires exposed in a top surface of said carrier;

connecting an integrated circuit chip to said top surface of said interposer and electrically connecting, electrically conductive pads exposed at a surface of said integrated circuit chip to said vias exposed in said top surface of said interposer;

forming one or more stress relief structures entirely within said interposer, said one or more stress relief structures either (i) not electrically connected to said vias of said interposer or to said electrically conductive pads of said integrated circuit chip or (ii) electrically connected to ground through said vias of said interposer or through said electrically conductive pads of said integrated circuit chip; and

wherein said one or more stress relief structures are in tensile stress.

9. The method of claim 8 , further including:

attaching said one or more stress relief structures to said interposer by solder connections.

10. The method of claim 8 , further including:

attaching said one or more stress relief structures to said interposer with adhesive.

11. The method of claim 8 , further including:

etching a first set of trenches extending from said top surface of said interposer into said interposer to a first depth,

filling said first trenches with an electrically conductive material;

said forming said one or more stress relief structure includes etching a second set of trenches extending from said top surface of said interposer into said interposer to a second depth, said second depth less than said first depth and filling said second trenches with stress relief material; and

thinning said interposer to expose said electrically conductive material in said first trenches at said bottom surface of said interposer.

12. The method of claim 8 , further including:

etching a first set of trenches extending from said top surface of said interposer into said interposer to a first depth;

etching a second set of trenches extending from said top surface of said interposer into said interposer to a second depth, said first depth greater than said second depth;

simultaneously filling said first and second trenches with an electrically conductive material to form said one or more stress relief structures in said second trenches; and

thinning said interposer to expose said electrically conductive material in said first trenches at said bottom surface of said interposer.

13. The method of claim 8 , wherein said one or more stress relief structures are positioned on regions of said interposer that are adjacent to a perimeter of said integrated circuit chip.

14. The method of claim 8 , wherein said one or more stress relief structures comprise a material selected from the group consisting of silicon, tungsten, ceramic, silicon dioxide, silicon nitride, tantalum, titanium, tantalum nitride, titanium nitride and Invar.

15. The method of claim 8 , wherein said integrated circuit chip is physically and electrically attached to said interposer by solder balls and wherein said interposer is physically and electrically attached to said carrier by solder balls.

16. The method of claim 8 , wherein said forming said one or more stress relief structures includes depositing one or more layers on said top surface of said interposer by sputtering, evaporation, electroless plating or electrical plating.

17. The method of claim 8 , wherein said forming said one or more stress relief structure includes depositing one or more layers on said bottom surface of said interposer by sputtering, evaporation, electroless plating or electrical plating.

18. The method of claim 8 , wherein said forming said stress relief structure includes (i) depositing one or more layers on said top surface of said interposer by sputtering, evaporation or electrochemical deposition and (ii) depositing one or more layers on said bottom surface of said interposer by sputtering, evaporation, electroless plating or electrical plating.

19. A structure, comprising:

a carrier;

a silicon interposer mechanically connected to a top surface of said carrier, said interposer having vias extending from a top surface of said interposer, through said interposer, to a bottom surface of said interposer, said vias that are exposed at said bottom surface of said interposer electrically connected to wires exposed in a top surface of said carrier;

an integrated circuit chip mechanically connected to said top surface of said interposer, electrically conductive pads exposed at a surface of said integrated circuit chip electrically connected to said vias exposed in said top surface of said interposer;

one or more stress relief structures formed entirely in said interposer, said one or more stress relief structures either (i) not electrically connected to said vias of said interposer or to said electrically conductive pads of said integrated circuit chip or (ii) electrically connected to ground through said vias of said interposer or through said electrically conductive pads of said integrated circuit chip; and

wherein said one or more stress relief structures are attached to said interposer by solder.