IP Library Granted Patent US 7,585,750
Granted Patent B2
US 7,585,750 · App. 11/861,233 · Granted Sep 8, 2009

Semiconductor package having through-hole via on saw streets formed with partial saw

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Quick Facts
Patent No.
US 7,585,750
App. No.
11/861,233
Granted
Sep 8, 2009
Kind
B2
Abstract

A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely through the wafer. The uncut portion of the saw street guides below the trench along a backside of the wafer maintains structural support for the semiconductor wafer. The trench is filled with organic material. Via holes are formed in the organic material. Traces are formed between the contact pads and via holes. Conductive material is deposited in the via holes to form metal vias. The uncut portion of the saw streets below the trench along the backside of the semiconductor wafer portion is removed. The semiconductor wafer is singulated along the saw street guides to separate the die.

Claims (54)

1. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw street guides between each die;

forming a trench in the saw street guides without using support material to support the semiconductor wafer, the trench extending partially but not completely through the semiconductor wafer, the uncut portion of the saw street guides below the trench along a backside of the semiconductor wafer being more than 60% of a thickness of the semiconductor wafer to maintain structural support for the semiconductor wafer without the support material during the processing steps of:

(a) filling the trench with organic material,

(b) forming a plurality of via holes in the organic material,

(c) forming traces between the contact pads and via holes, and

(d) depositing conductive material in the via holes to form metal vias;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion;

applying dicing tape to the backside of the semiconductor wafer;

cutting through the metal vias to the dicing tape; and

singulating the semiconductor wafer along the saw street guides by removing the dicing tape to separate the die into individual units.

2. The method of claim 1 , wherein at least one metal via is formed between the contact pads on adjacent die.

3. The method of claim 2 , wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

4. The method of claim 1 , wherein two metal vias are formed side by side between the contact pads on adjacent die.

5. The method of claim 4 , wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

6. The method of claim 1 , wherein the trench is less than a width of the saw street guides.

7. The method of claim 1 , wherein the trench is centered about the saw street guides.

8. The method of claim 1 , wherein the die are stackable and connected by the metal vias when stacked.

9. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw street guides between each die;

forming a trench in the saw street guides without using support material to support the semiconductor wafer, the trench extending partially through the semiconductor wafer, the uncut portion of the saw street guides below the trench along a backside of the semiconductor wafer having sufficient thickness to maintain structural support for the semiconductor wafer without the support material during the processing steps of:

(a) filling the trench with organic material,

(b) forming a plurality of via holes in the organic material,

(c) forming traces between the contact pads and via holes, and

(d) depositing conductive material in the via holes to form metal vias;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion;

applying wafer support material to the backside of the semiconductor wafer;

cutting through the metal vias to the wafer support material; and

singulating the semiconductor wafer along the saw street guides by removing the wafer support material to separate the die into individual units.

10. The method of claim 9 , wherein at least one metal via is formed between the contact pads on adjacent die.

11. The method of claim 10 , wherein the semiconductor wafer is singulated through the at least one metal via to form metal vias electrically connected to the contact pads by the traces.

12. The method of claim 9 , wherein two metal vias are formed side by side between the contact pads on adjacent die.

13. The method of claim 12 , wherein the semiconductor wafer is singulated along the saw street guides between the two metal vias to form metal vias electrically connected to the contact pads by the traces.

14. The method of claim 9 , wherein the trench is less than a width of the saw street guides.

15. The method of claim 9 , wherein the trench is centered about the saw street guides.

16. The method of claim 9 , wherein the die are stackable and connected by the metal vias when stacked.

17. The method of claim 9 , wherein the uncut portion of the saw street guides below the trench along the backside of the semiconductor wafer being more than 60% of a thickness of the semiconductor wafer.

18. A method of forming through-hole vias in a semiconductor wafer, comprising:

forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die, the semiconductor wafer having saw Street guides between each die;

forming a trench in the saw street guides without using support material to support the semiconductor wafer, the trench extending partially through the semiconductor wafer, the uncut portion of the saw street guides below the trench along a backside of the semiconductor wafer having sufficient thickness to maintain structural support for the semiconductor wafer without the support material during the processing steps of:

(a) filling the trench with organic material,

(b) forming a plurality of via holes in the organic material,

(c) depositing conductive material in the via holes to form conductive vias, and

(d) forming conductive traces between the contact pads and conductive vias;

removing the uncut portion of the saw street guide below the trench along the backside of the semiconductor wafer portion; and

singulating the semiconductor wafer along the saw street guides to separate the die into individual units.

19. The method of claim 18 , wherein at least one conductive via is formed between the contact pads on adjacent die.

20. The method of claim 19 , wherein the semiconductor wafer is singulated through the at least one conductive via to form conductive vias electrically connected to the contact pads by the conductive traces.

21. The method of claim 18 , wherein two conductive vias are formed side by side between the contact pads on adjacent die.

22. The method of claim 21 , wherein the semiconductor wafer is singulated along the saw street guides between the two conductive vias to form conductive vias electrically connected to the contact pads by the conductive traces.

23. The method of claim 18 , wherein the trench is less than a width of the saw street guides.

24. The method of claim 18 , wherein the trench is centered about the saw street guides.

25. The method of claim 18 , wherein the die are stackable and connected by the conductive vias when stacked.

26. The method of claim 18 , wherein the uncut portion of the saw street guides below the trench along the backside of the semiconductor wafer being more than 60% of a thickness of the semiconductor wafer.

Assignments (6)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2007
From: DO, BYUNG TAI; KUAN, HEAP HOE; CHUA, LINDA PEI EE
To: STATS CHIPPAC, LTD.
Reel/Frame 019876/0394 →