Granted Patent B1

US 7,515,469 · App. 11/862,436 · Granted Apr 7, 2009

Abstract

Claims (37)

1. A column redundancy system for a non-volatile memory, the system comprising:

a separate companion controller chip for controlling operational modes of the non-volatile memory chip, the separate companion controller chip including a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells;

column redundancy match logic configured to compare user input addresses for the non-volatile memory to addresses of defective non-volatile memory cells stored in a column redundancy RAM memory array and configured to provide a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell stored in the column redundancy RAM memory array; and

column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, configured to dynamically substitute correct data associated with a defective non-volatile memory cell into an I/O data bit stream of a non-volatile memory chip.

2. The column redundancy system of claim 1 wherein the column redundancy replacement logic includes column redundancy replacement logic configured to program the non-volatile memory with redundant data for defective non-volatile memory cells, said redundant data stored in redundant columns of the non-volatile memory; and

wherein the column redundancy replacement logic includes column redundancy replacement logic configured to read the non-volatile memory with redundant data for defective non-volatile memory cells, said redundant data stored in redundant columns of the non-volatile memory.

3. The column redundancy system of claim 1 wherein the column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, substitutes correct data associated with a defective non-volatile memory cell into an I/O data bit stream of the non-volatile memory chip for a program mode of operation, a read mode of operation, and an erase mode of operation for the non-volatile memory chip.

4. The column redundancy system of claim 1 wherein the column redundancy match logic compares addresses for a portion of a memory data byte stored in the non-volatile memory.

5. The column redundancy system of claim 4 wherein the portion of a memory data byte stored in the non-volatile memory is a nibble.

6. The column redundancy system of claim 1 wherein the addresses stored in the redundancy RAM memory array of defective non-volatile memory cells are transferred from fused addresses of defective non-volatile memory cells, said addresses originally stored in the non-volatile memory chip.

7. The column redundancy system of claim 1 wherein the non-volatile memory chip is a FLASH memory chip.

8. The column redundancy system of claim 1 wherein each memory cell of the column redundancy RAM memory array includes an input transmission gate activated by a write command signal, a cross-coupled inverter latch configured to store a bit, and a gated output circuit that is activated by a read command signal.

9. A column redundancy system for a non-volatile memory, the system comprising:

a non-volatile memory chip providing an I/O data bit stream for programming data into or for reading data out of a non-volatile memory array that includes column redundancy fuses for storing addresses of defective non-volatile memory cells;

a separate companion controller chip configured to control operational modes of the non-volatile memory chip, the separate companion controller chip including a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells;

column redundancy match logic configured to compare user input addresses for the non-volatile memory to the addresses of defective non-volatile memory cells stored in the column redundancy RAM memory array and configured to provide a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array; and

column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, configured to dynamically substitute correct data associated with a defective non-volatile memory cell into an I/O data bit stream of the non-volatile memory chip.

10. The column redundancy system of claim 9 wherein the column redundancy replacement logic includes column redundancy replacement logic for programming the non-volatile memory with redundant data for defective non-volatile memory cells, said redundant data stored in redundant columns of the non-volatile memory.

11. The column redundancy system of claim 9 wherein the column redundancy replacement logic includes column redundancy replacement logic for reading the non-volatile memory with redundant data for defective non-volatile memory cells, said redundant data stored in redundant columns of the non-volatile memory.

12. The column redundancy system of claim 9 wherein the column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, substitutes correct data associated with a defective non-volatile memory cell into an I/O data bit stream of the non-volatile memory chip for a program mode of operation, a read mode of operation, and an erase mode of operation for the non-volatile memory chip.

13. The column redundancy system of claim 9 wherein the column redundancy match logic compares addresses for a portion of a memory data byte stored in the non-volatile memory.

14. The column redundancy system of claim 13 wherein the portion of a memory data byte stored in the non-volatile memory is a nibble.

15. The column redundancy system of claim 9 wherein the addresses stored in the redundancy RAM memory array of defective non-volatile memory cells are transferred from fused addresses of defective non-volatile memory cells originally stored in the non-volatile memory chip.

16. The column redundancy system of claim 9 wherein the non-volatile memory chip is a FLASH memory chip.

17. A method of providing column redundancy for a non-volatile memory chip, the method comprising the steps of:

controlling operational modes of the non-volatile memory chip with a separate companion controller chip;

storing addresses of defective non-volatile memory cells in a column redundancy RAM memory array of the separate companion controller chip;

comparing, with redundancy match logic, user input addresses for the non-volatile memory to the addresses of defective non-volatile memory cells, said addresses stored in the column redundancy RAM memory array;

providing from the redundancy match logic a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array; and

dynamically substituting, with column redundancy replacement logic in response to a match output signal from the column redundancy match logic, correct data associated with the defective non-volatile memory cell into an I/O data bit stream of the non-volatile memory chip.

18. The method of claim 17 including programming the non-volatile memory, using the column redundancy replacement logic, with redundant data for defective non-volatile memory cells, said redundant data stored in redundant columns of the non-volatile memory; and

reading the non-volatile memory, using the column redundancy replacement logic, with redundant data for defective non-volatile memory cells being stored in redundant columns of the non-volatile memory.

19. The method of claim 17 including substituting correct data associated with a defective non-volatile memory cell into the I/O data bit stream of the non-volatile memory chip for a program mode of operation, a read mode of operation, and an erase mode of operation for the non-volatile memory chip, using the column redundancy replacement logic, in response to a match output signal from the column redundancy match logic.

20. The method of claim 17 including comparing, with the column redundancy match logic, addresses for a portion of a memory data byte stored in the non-volatile memory.

21. The method of claim 20 wherein the portion of a memory data byte stored in the non-volatile memory is a nibble.

22. The method of claim 17 including transferring addresses stored in the redundancy RAM memory array from fused addresses of defective non-volatile memory cells originally stored in the non-volatile memory chip.

23. The method of claim 17 wherein the non-volatile memory chip is a FLASH memory chip.

Assignments (18)