Line-reflect-reflect match calibration
View Patent ↗A method of compensating a calibration for a vector network analyzer includes performing calibrations on at least a pair of ports to determine error terms associated with each port wherein at least one of the error terms is based upon selecting the reactance of the load standard from a set of potential values in a manner such that the reference reactance errors are reduced.
1. A method of calibrating a port of a vector network analyzer comprising the steps of:
(a) determining a magnitude of an expected reflection for a reference open standard;
(b) estimating a plurality of load inductance values for a load;
(c) calculating a magnitude of an estimated reflection for each of said plurality of estimated load inductance values;
(d) determining a difference between said magnitude of said expected reflection for said reference open standard and said magnitude of said estimated reflection for each of said estimated load inductance values; and
(e) selecting one estimated load inductance value that minimizes a sum of said difference between said magnitude of said expected reflection for said reference open standard and said magnitude of said estimated reflection for said estimated load inductance for a plurality of frequencies; and
(f) calibrating a port of said vector network analyzer to correct a measurement at said port for an effect of said one estimated load inductance value.
2. The method of claim 1 wherein said method accounts for differences between the load measured at a probe-tip reference plane and measured at a center-of-thru reference plane.
3. The method of claim 1 wherein each of said plurality of estimated load inductance values comprises a reactance of said load.
4. The method of claim 1 wherein for each of said estimated load inductance values a load impedance at a probe tip is computed.
5. The method of claim 4 wherein each computed load impedance at said probe tip is translated to a thru-center reference plane.
6. The method of claim 5 wherein at least one error term is renormalized based upon said translated computed load impedance.