Non-volatile look-up table for an FPGA
View Patent ↗A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A one input non-volatile-memory-transistor based lookup table is coupled to each of the n data inputs of the multiplexer. The multiplexer has X inputs wherein n=2 X as is known in the art. A sense amplifier is coupled to the output of the multiplexer.
1. A non-volatile-memory-transistor based lookup table for an FPGA, comprising:
a VCC power supply;
a ground supply;
X lookup table inputs wherein X is a positive integer;
a lookup table output;
a multiplexer having X address inputs, Y data inputs, and an output, wherein each address input is coupled to a separate one of said lookup table inputs, the output is coupled to the lookup table output, and Y=2X;
an additional lookup table input;
an inverting circuit with an input coupled to said additional lookup table input and an output;
a first group of Y transistors programmably coupling said VCC supply and separate ones of the Y data inputs of said multiplexer;
a second group of Y transistors programmably coupling said additional lookup table input and separate ones of the Y data inputs of said multiplexer;
a third group of Y transistors programmably coupling the output of said inverting circuit and separate ones of the Y data inputs of said multiplexer; and
a fourth group of Y transistors programmably coupling said ground supply and separate ones of the Y data inputs of said multiplexer.
2. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 1 , further comprising:
a sense amplifier coupled between the output of said multiplexer and said lookup table output.
3. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 2 , wherein:
said first group of Y transistors are non-volatile-memory transistors;
said second group of Y transistors are non-volatile-memory transistors;
said third group of Y transistors are non-volatile-memory transistors; and
said fourth group of Y transistors are non-volatile-memory transistors.
4. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 2 , wherein:
said first group of Y transistors are MOS transistors;
said second group of Y transistors are MOS transistors;
said third group of Y transistors are MOS transistors; and
said fourth group of Y transistors are MOS transistors.
5. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 2 , wherein:
said first group of Y transistors are n-channel MOS transistors;
said second group of Y transistors are n-channel MOS transistors;
said third group of Y transistors are n-channel MOS transistors; and
said fourth group of Y transistors are n-channel MOS transistors.
6. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 1 , wherein:
said first group of Y transistors are non-volatile-memory transistors;
said second group of Y transistors are non-volatile-memory transistors;
said third group of Y transistors are non-volatile-memory transistors; and
said fourth group of Y transistors are non-volatile-memory transistors.
7. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 1 , wherein:
said first group of Y transistors are MOS transistors;
said second group of Y transistors are MOS transistors;
said third group of Y transistors are MOS transistors; and
said fourth group of Y transistors are MOS transistors.
8. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 1 , wherein:
said first group of Y transistors are n-channel MOS transistors;
said second group of Y transistors are n-channel MOS transistors;
said third group of Y transistors are n-channel MOS transistors; and
said fourth group of Y transistors are n-channel MOS transistors.
9. A non-volatile-memory-transistor based lookup table for an FPGA, comprising:
a VCC power supply;
a ground supply;
X lookup table inputs wherein X is a positive integer;
a lookup table output;
a multiplexer having X address inputs, Y data inputs, and an output, wherein each address input is coupled to a separate one of said lookup table inputs, the output is coupled to the lookup table output, and Y=2X;
a first additional lookup table input;
a second additional lookup table input;
a first group of Y transistors programmably coupling said VCC supply and separate ones of the Y data inputs of said multiplexer;
a second group of Y transistors programmably coupling said first additional lookup table input and separate ones of the Y data inputs of said multiplexer;
a third group of Y transistors programmably coupling said second additional lookup table input and separate ones of the Y data inputs of said multiplexer; and
a fourth group of Y transistors programmably coupling said ground supply and separate ones of the Y data inputs of said multiplexer.
10. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 9 , wherein:
said second additional lookup table input may be configured to carry the binary complement of said first additional lookup table input.
11. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 10 , further comprising:
a sense amplifier coupled between the output of said multiplexer and said lookup table output.
12. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 11 , wherein:
said first group of Y transistors are non-volatile-memory transistors;
said second group of Y transistors are non-volatile-memory transistors;
said third group of Y transistors are non-volatile-memory transistors; and
said fourth group of Y transistors are non-volatile-memory transistors.
13. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 11 , wherein:
said first group of Y transistors are MOS transistors;
said second group of Y transistors are MOS transistors;
said third group of Y transistors are MOS transistors; and
said fourth group of Y transistors are MOS transistors.
14. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 11 , wherein:
said first group of Y transistors are n-channel MOS transistors;
said second group of Y transistors are n-channel MOS transistors;
said third group of Y transistors are n-channel MOS transistors; and
said fourth group of Y transistors are n-channel MOS transistors.
15. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 10 , wherein:
said first group of Y transistors are non-volatile-memory transistors;
said second group of Y transistors are non-volatile-memory transistors;
said third group of Y transistors are non-volatile-memory transistors; and
said fourth group of Y transistors are non-volatile-memory transistors.
16. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 10 , wherein:
said first group of Y transistors are MOS transistors;
said second group of Y transistors are MOS transistors;
said third group of Y transistors are MOS transistors; and
said fourth group of Y transistors are MOS transistors.
17. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 10 , wherein:
said first group of Y transistors are n-channel MOS transistors;
said second group of Y transistors are n-channel MOS transistors;
said third group of Y transistors are n-channel MOS transistors; and
said fourth group of Y transistors are n-channel MOS transistors.
18. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 9 , wherein:
said first group of Y transistors are non-volatile-memory transistors;
said second group of Y transistors are non-volatile-memory transistors;
said third group of Y transistors are non-volatile-memory transistors; and
said fourth group of Y transistors are non-volatile-memory transistors.
19. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 9 , wherein:
said first group of Y transistors are MOS transistors;
said second group of Y transistors are MOS transistors;
said third group of Y transistors are MOS transistors; and
said fourth group of Y transistors are MOS transistors.
20. A non-volatile-memory-transistor based lookup table for an FPGA according to claim 9 , wherein:
said first group of Y transistors are n-channel MOS transistors;
said second group of Y transistors are n-channel MOS transistors;
said third group of Y transistors are n-channel MOS transistors; and
said fourth group of Y transistors are n-channel MOS transistors.