Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a through substrate via (TSV) in the substrate, the TSV being formed by first etching a trench into a first surface of the substrate;

lining the first surface of the substrate and the trench with a first insulating layer;

patterning a resistive layer on the first insulating layer;

patterning a first conductive layer on the first insulating layer, wherein patterns of the first conductive layer form plating within the TSV and simultaneously form a first terminal of an analog circuit formed on the first surface of the substrate, the patterned resistive layer forming portions of the analog circuit;

depositing a second conductive layer on the first conductive layer, the first conductive layer providing adhesion of the second conductive layer;

grinding a second surface of the substrate to expose the TSV on the second surface of the substrate;

forming a second insulating layer over the second surface of the substrate;

forming an under bump metallization (UBM) layer on the second surface of the substrate in electrical contact with the first and second conductive layers in the TSV, wherein the exposed TSV provides alignment of the UBM layer directly opposite the exposed TSV on the second surface of the substrate;

depositing solder material on the UBM layer; and

reflowing the solder material to form a solder bump, wherein the analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

2. The method of claim 1 , further including forming a plurality of active devices on the substrate.

3. The method of claim 1 , further including forming a redistribution layer between the TSV and UBM.

4. The method of claim 1 , wherein the analog circuit includes an inductor, metal-insulator-metal capacitor, or resistor.

5. The method of claim 4 , wherein the analog circuit includes an inductor that is made with copper and is deposited at approximately the same time as the deposition of the second conductive layer in the TSV.

6. The method of claim 1 , further including forming a wire bond on a top surface of the substrate.

7. The method of claim 1 , further including depositing polymer glue over the substrate and bonding a chip carrier to the polymer glue.

8. A method of making a semiconductor device, comprising:

providing a substrate;

etching a via through a first surface of the substrate, the via containing a first conductive material patterned during a first process;

forming a first passive device on a first surface of the substrate, wherein forming the first passive device includes forming first and second terminals of the first passive device using a portion of the first conductive material patterned during the first process, the first and second terminals of the first passive device being aligned in a parallel orientation with respect to the first surface of the substrate;

forming a second passive device on the first surface of the substrate, wherein forming the second passive device includes,

forming a first terminal of the second passive device using a portion of the first conductive material patterned during the first process; and

forming a second terminal of the second passive device using a portion of a second conductive material patterned during a second process, the first and second terminals of the second passive device being aligned in a stacked orientation with respect to the first surface of the substrate; and

forming an interconnect structure on a second surface of the substrate in electrical contact with the conductive material in the via, wherein the first and second passive devices electrically connect through the via to the interconnect structure on the second surface of the substrate.

9. The method of claim 8 , wherein forming an interconnect structure on a second surface of the substrate includes:

forming an under bump metallization layer in electrical contact with the via; and

forming a solder bump on the under bump metallization layer.

10. The method of claim 8 , further including forming a redistribution layer between the via and interconnect structure.

11. The method of claim 8 , wherein the first passive device is an inductor.

12. The method of claim 11 , wherein the inductor is made with copper.

13. The method of claim 8 , wherein the second passive device is a metal-insulator-metal capacitor.

14. The method of claim 8 , wherein the first passive device is a resistor.

15. The method of claim 8 , further including forming a wire bond on a top surface of the substrate.

16. A method of making a semiconductor device, comprising:

providing a substrate;

forming a passive device on a first surface of the substrate;

forming a via through the substrate, the via being oriented along an axis that is perpendicular to the first surface of the substrate;

depositing conductive material in the via, the conductive material also being deposited to form a first terminal of the passive device; and

forming an interconnect structure on a second surface of the substrate in electrical contact with the conductive material in the via, wherein forming the interconnect structure includes,

forming an under bump metallization layer in electrical contact with the via; and

forming a solder bump on the under bump metallization layer, the solder bump being offset from the axis of the via.

17. The method of claim 16 , wherein the passive device is in electrical contact with the conductive material in the via.

18. The method of claim 16 , further including forming a redistribution layer between the via and interconnect structure.

19. The method of claim 16 , wherein the passive device is an inductor, capacitor, or resistor.