Granted Patent B2

US 8,054,911 · App. 11/950,361 · Granted Nov 8, 2011

Abstract

Claims (31)

1. A method for edge formation of signals that are output to a bus line of a bus system, the method comprising:

detecting a high-frequency interference level on the bus line of the bus system;

increasing an edge steepness of the output signals when the high-frequency interference level on the bus line increases; and

reducing the edge steepness of the output signals when the high-frequency interference level on the bus line decreases;

wherein with an increase in the edge steepness of the signals, one or more of a rising signal edge and a falling signal edge is delayed by a time period, so that the signal edge of a signal with the increased edge steepness reaches a threshold value, assigned to a logic level, at a same time as the signal edge of a signal with a normal edge steepness.

2. The method according to claim 1 , wherein the edge steepness is increased continuously with an increasing high-frequency interference level on the bus line.

3. The method according to claim 1 , wherein the edge steepness is increased stepwise from a first edge steepness value to at least one second edge steepness value, when the high-frequency interference level exceeds at least one first high-frequency interference level threshold.

4. The method according to claim 1 , wherein, to detect the high-frequency interference level, frequencies of interference signals within a frequency range of from 500 kHz to 5 GHz, 900 kHz to 3 GHz, or 1 MHz to 1 GHz, are taken into account.

5. The method according to claim 1 , wherein the detection of the high-frequency interference level further comprises the step of rectifying the interference signals present on the bus line.

6. The method according to claim 5 , wherein the detection of the high-frequency interference level further comprises the step of filtering the rectified high-frequency interference signals, particularly the formation of an average from the rectified high frequency interference signals.

7. The method according to claim 1 , wherein, in the case of the increase in the edge steepness of the signals, the one or more of the rising signal edge and the falling signal edge is delayed by such a time period that for a receiver of the signals, the one or more of the rising signal edge and the falling signal edge can be received at an unchanged point in time.

8. The method according to claim 1 , wherein the bus system is a LIN bus system.

9. A transmitter/receiver component for a bus system comprising:

a driver transistor that is looped between a bus line of the bus system and a reference potential and is used to output signals on the bus line;

a control unit for the driver transistor;

a high-frequency interference detector configured to detect a high-frequency interference level on the bus line of the bus system; and

a delay unit, which is configured in such a way that with an increase in an edge steepness of the signals, one or more of a rising signal edge and a falling signal edge is delayed by a time period so that the signal edge of a signal with the increased edge steepness reaches a threshold value, assigned to a logic level, at an identical time as the signal edge of a signal with a normal edge steepness;

wherein the control unit is configured to control the driver transistor depending on the detected high-frequency interference level so that an edge steepness of the output signals increases when the high-frequency interference level on the bus line increases, and so that the edge steepness of the output signals decreases when the high-frequency interference level on the bus line decreases.

10. The transmitter/receiver component according to claim 9 , further comprising:

a first controllable current source that is looped between a supply voltage and a gate terminal of the driver transistor; and

a second controllable current source that is looped between the gate terminal of driver transistor and a reference potential.

11. The transmitter/receiver component according to claim 10 , wherein a filter or a lowpass filter for interference suppression is looped between the gate terminal of the driver transistor and the first controllable current source and the second controllable current source.

12. The transmitter/receiver component according to claim 9 , further comprising:

a third controllable current source that is looped between a supply voltage and a gate terminal of the driver transistor; and

a fourth controllable current source that is looped between the gate terminal of driver transistor and a reference potential,

wherein the third controllable current source and the fourth controllable current source are controlled by the control unit to change the edge steepness of the output signals.

13. The transmitter/receiver component according to claim 9 , wherein the delay unit is further configured in such a way that in the case of the increase in the edge steepness of the signals, the one or more of the rising signal edge and the falling signal edge is delayed by such a time period that for a receiver of the signals, the rising signal edge and/or falling signal edge can be received at an unchanged point in time.

14. The transmitter/receiver component according to claim 9 , wherein the high frequency interference detector comprises a rectifier that rectifies high-frequency interference signals on the bus line.

15. The transmitter/receiver component according to claim 14 , wherein the high frequency interference detector comprises a filter, which filters the rectified high-frequency interference signals.

16. The transmitter/receiver component according to claim 15 , wherein the filter comprises an averager that forms an average from the rectified high-frequency interference signals.

17. The transmitter/receiver component according to claim 9 , wherein the bus system is a LIN bus system, and wherein the transmitter/receiver component forms a LIN bus driver.

Assignments (19)