PWM controller having drive control with input voltage sensing and method therefor
View Patent ↗In one embodiment, a PWM controller includes a circuit operably coupled to inhibit a drive signal responsively to a bulk input voltage remaining at a low value for a time interval and to re-enable the drive signal subsequently to the time interval responsively to the bulk input voltage increasing to greater than the first value subsequently to the time interval. In another embodiment, a method of forming a PWM controller includes configuring the PWM controller to use a clock signal to form a drive signal and to sense a bulk input voltage decreasing to no greater than a first value and to disable the drive signal without disabling the clock signal responsively to the bulk input voltage remaining no greater than the first value for a time interval.
1. A PWM controller comprising:
a first circuit configured to provide a drive signal used to regulate an output voltage to a desired value;
a second circuit operably coupled to detect a bulk input voltage decreasing to a first value and responsively form a first control signal; and
a third circuit operably coupled to receive the first control signal and to disable the drive signal responsively to the bulk input voltage remaining no greater than the first value for a time interval and operably coupled to inhibit disabling the drive signal and to reset the time interval responsively to the bulk input voltage increasing to a second value that is greater than the first value before the time interval expires, the third circuit configured to re-enable the drive signal subsequently to the time interval responsively to the bulk input voltage increasing to the second value subsequently to the time interval.
2. The PWM controller of claim 1 wherein the PWM controller is operably coupled to increase a maximum allowable duty cycle of the drive signal responsively to the first control signal.
3. The PWM controller of claim 2 further including a duty cycle control circuit that forms a duty cycle control signal that is used to limit a maximum allowable duty cycle of the drive signal to a first duty cycle value and further including logic that negates the duty cycle control signal responsively to the first control signal.
4. The PWM controller of claim 2 further including a duty cycle control circuit that forms a maximum duty cycle control signal having a first control value that limits a maximum allowable duty cycle of the drive signal to a first duty cycle value responsively to a first state of the first control signal and limits the maximum allowable duty cycle to a second duty cycle value responsively to a second state of the first control signal.
5. The PWM controller of claim 1 wherein the third circuit includes a timer that is coupled to start the time interval responsively to a first state of the first control signal and to reset the time interval responsively to a second state of the first control signal.
6. The PWM controller of claim 1 wherein the second circuit includes a comparator coupled to compare a signal that is representative of the bulk voltage to a reference signal.
7. The PWM controller of claim 6 wherein the third circuit includes a timer that is coupled to start the time interval responsively to a first state of the comparator and to reset the time interval responsively to a second state of the comparator.
8. A method of forming a PWM controller comprising:
configuring an oscillator circuit to form a clock signal having a period;
configuring the PWM controller to use the clock signal to form a drive signal used to regulate an output voltage to a desired value, the drive signal having the period of the clock signal;
configuring the PWM controller to sense a bulk input voltage decreasing to no greater than a first value and to disable the drive signal without disabling the clock signal responsively to the bulk input voltage remaining no greater than the first value for a time interval wherein the PWM controller continues forming drive signals during the time interval; and
configuring the PWM controller to not disable the drive signal responsively to the bulk input voltage increasing to greater than the first value at any time prior to the time interval expiring.
9. The method of claim 8 further including configuring the PWM controller to increase a maximum allowable duty cycle of the drive signal from a first duty cycle value to a second duty cycle value responsively to the bulk input voltage decreasing to no greater than the first value.
10. The method of claim 9 further including configuring the PWM controller to decrease the maximum allowable duty cycle to the first value responsively to the bulk input voltage increasing to greater than the first value.
11. The method of claim 8 wherein configuring the PWM controller to sense the bulk input voltage includes configuring the PWM controller to form the time interval to be no less than approximately a period of a ripple voltage of the bulk input voltage.
12. The method of claim 8 wherein configuring the PWM controller to sense the bulk input voltage includes configuring the PWM controller to form the time interval to be no less than approximately ten milli-seconds.
13. The method of claim 8 further including configuring the PWM controller to re-enable the drive signal subsequently to the time interval responsively to the bulk input voltage increasing to a second value that is greater than the first value subsequently to the time interval.
14. The method of claim 8 further including resetting the time interval responsively to the bulk input voltage increasing to greater than the first value at any time prior to the time interval expiring.