Integrated circuit system with memory system
View Patent ↗A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
1. A method for forming an integrated circuit system comprising:
forming a memory section having a spacer with a substrate;
forming an outer doped region of the memory section in the substrate not below the memory section;
forming a barrier metal layer over the spacer lateral to a sidewall of the memory section; and
forming a metal plug over the outer doped region and the barrier metal layer;
wherein the outer doped region is wider than an inner doped region of the memory section and the substrate is not doped under the spacer.
2. The method as claimed in claim 1 wherein forming the barrier metal layer includes forming titanium.
3. The method as claimed in claim 1 wherein forming the metal plug includes forming a tungsten plug.
4. The method as claimed in claim 1 wherein forming the outer doped region includes forming a source region.
5. The method as claimed in claim 1 further comprising forming an electronic system or a subsystem with the integrated circuit system.
6. A method for forming an integrated circuit system comprising:
forming a memory section having a charge storage stack and a spacer with a substrate;
forming an outer doped region of the memory section in the substrate not below the memory section;
forming a barrier metal layer over the spacer lateral to a sidewall of the memory section; and
forming a tungsten plug over the outer doped region and on the barrier metal layer;
wherein the outer doped region is wider than an inner doped region of the memory section and the substrate is not doped under the spacer.
7. The method as claimed in claim 6 wherein forming the memory section having the charge storage stack includes forming a silicon rich nitride portion.
8. The method as claimed in claim 6 wherein forming the memory section includes forming memory cells in a series.
9. The method as claimed in claim 6 further comprising connecting a source line and the tungsten plug.
10. The method as claimed in claim 6 further comprising forming a silicide layer between the tungsten plug and the outer doped region.
11. An integrated circuit system comprising:
a memory section having a spacer with a substrate;
an outer doped region of the memory section in the substrate not below the memory section;
a barrier metal layer over the spacer lateral to a sidewall of the memory section; and
a metal plug over the outer doped region and the barrier metal layer;
wherein the outer doped region is wider than an inner doped region of the memory section and the substrate is not doped under the spacer.
12. The system as claimed in claim 11 wherein the barrier metal layer includes titanium.
13. The system as claimed in claim 11 wherein the metal plug includes a tungsten plug.
14. The system as claimed in claim 11 wherein the outer doped region includes a source region.
15. The system as claimed in claim 11 further comprising an electronic system or a subsystem with the integrated circuit system.
16. The system as claimed in claim 11 wherein:
the memory section has a charge storage stack and the spacer over the substrate;
the outer doped region of the memory section in the substrate is not below the memory section;
the barrier metal layer includes titanium and is over the spacer; and
the metal plug is a tungsten plug over the outer doped region and on the barrier metal layer.
17. The system as claimed in claim 16 wherein the memory section having the charge storage stack includes a silicon rich nitride portion.
18. The system as claimed in claim 16 wherein the memory section includes memory cells in a series.
19. The system as claimed in claim 16 further comprising a source line connected with the tungsten plug.
20. The system as claimed in claim 16 further comprising a silicide layer between the tungsten plug and the outer doped region.