Non-volatile memory array having drain-side segmentation for an FPGA device
View Patent ↗A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
1. A non-volatile memory array for a field-programmable-gate-array device having drain-side segmentation and comprising:
a plurality of memory cells arranged as an array of rows and columns, the array divided into a plurality of segments, each segment including a plurality of rows, each memory cell including a non-volatile memory transistor having a source, a drain, a floating gate, and a control gate, the source of each non-volatile memory transistor in each segment coupled together to a common source line, the non-volatile memory transistors in each segment being formed in a well associated only with that segment;
at least one switch transistor associated with each non-volatile memory transistor, the at least one switch transistor having a source, a drain, a floating gate and a control gate and wherein each non-volatile memory transistor shares a floating gate with its associated at least one switch transistor;
a column line associated with each column in the array;
a column segment line associated with each segment of the array, each column segment line coupled to the drains of each non-volatile memory transistor in the segment;
a segment select transistor coupled between each column segment line and its associated column line; and
a high-voltage driver transistor coupled to each column line.
2. The non-volatile memory array of claim 1 wherein the sources of non-volatile memory transistors in adjacent columns are coupled to the same common source line.
3. The non-volatile memory array of claim 2 wherein each common source line is coupled to a source-bias transistor.
4. The non-volatile memory array of claim 3 wherein each source-bias transistor is coupled to ground.
5. The non-volatile memory array of claim 4 wherein the source-bias transistors associated with segments that include non-volatile memory transistors in the same rows are all controlled by a single gate line.
6. The non-volatile memory array of claim 1 wherein the non-volatile memory transistors in a single segment in adjacent pairs of odd-even columns are formed in the same well.
7. The non-volatile memory array of claim 6 wherein the non-volatile memory transistors are n-channel MOS transistors and the well is a p-well.
8. The non-volatile memory array of claim 1 wherein the control gates all non-volatile memory transistors and all of the least one switch transistors in a single row of the array are coupled together.
9. The non-volatile memory array of claim 1 wherein all of the at least one switch transistors associated with non-volatile memory transistors in a segment of a column of the array are formed in a single well.
10. The non-volatile memory array of claim 9 wherein all of the at least one switch transistors are n-channel MOS transistors and the well is a p-well.
11. The non-volatile memory array of claim 1 wherein the sources of non-volatile memory transistors in adjacent columns of the same segment are coupled to the same common source line.
12. The non-volatile memory array of claim 11 wherein each common source line is coupled to a source-bias transistor.
13. The non-volatile memory array of claim 12 wherein each source-bias transistor is coupled to ground.
14. The non-volatile memory array of claim 12 wherein the source-bias transistors associated with segments that include non-volatile memory transistors in the same rows are all controlled by a single gate line.
15. A non-volatile memory array for a field-programmable-gate-array device having drain-side segmentation and comprising:
a plurality of memory cells arranged as an array of rows and columns, the array divided into a plurality of segments, each segment including a plurality of rows, each memory cell including a non-volatile memory transistor having a source, a drain, a floating gate, and a control gate, the source of each non-volatile memory transistor in each segment coupled together to a segment source line, the non-volatile memory transistors in each segment being formed in a well associated only with that segment;
at least one switch transistor associated with each non-volatile memory transistor, the at least one switch transistor having a source, a drain, a floating gate and a control gate and wherein each non-volatile memory transistor shares a floating gate with its associated at least one switch transistor;
a plurality of column lines associated with the array, neighboring ones of the non-volatile memory transistors in adjacent pairs share a common column line;
a column segment line associated with each segment of the array, each column segment line coupled to the drains of each non-volatile memory transistor in the segment;
a segment select transistor coupled between each column segment line and its associated column line; and
a high-voltage driver transistor coupled to each column line.
16. The non-volatile memory array of claim 15 wherein the sources of non-volatile memory transistors in adjacent columns are coupled to the same segment source line.
17. The non-volatile memory array of claim 16 wherein each segment source line is coupled to a source-bias transistor.
18. The non-volatile memory array of claim 17 wherein each source-bias transistor is coupled to ground.
19. The non-volatile memory array of claim 18 wherein the source-bias transistors associated with segments that include non-volatile memory transistors in the same rows are all controlled by a single gate line.
20. The non-volatile memory array of claim 15 wherein the non-volatile memory transistors in a single segment in adjacent pairs of odd-even columns are formed in the same well.
21. The non-volatile memory array of claim 20 wherein the non-volatile memory transistors are n-channel MOS transistors and the well is a p-well.
22. The non-volatile memory array of claim 15 wherein the control gates all non-volatile memory transistors and all of the least one switch transistors in a single row of the array are coupled together.
23. The non-volatile memory array of claim 15 wherein all of the at least one switch transistors associated with non-volatile memory transistors in a segment of a column of the array are formed in a single well.
24. The non-volatile memory array of claim 23 wherein all of the at least one switch transistors are n-channel MOS transistors and the well is a p-well.
25. The non-volatile memory array of claim 15 wherein the sources of non-volatile memory transistors in adjacent columns of the same segment are coupled to the same segment source line.
26. The non-volatile memory array of claim 25 wherein each segment source line is coupled to a source-bias transistor.
27. The non-volatile memory array of claim 26 wherein each source-bias transistor is coupled to ground.
28. The non-volatile memory array of claim 26 wherein the source-bias transistors associated with segments that include non-volatile memory transistors in the same rows are all controlled by a single gate line.