Flexible carry scheme for field programmable gate arrays
View Patent ↗A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.
1. A logic module for a field programmable gate array integrated circuit device including:
a logic circuit programmable to implement an adder bit slice, the logic circuit including a logic function generator circuit, a first circuit node and a second circuit node, wherein the first circuit node is coupled to a carry-generate output of the adder bit slice and the second circuit node is coupled to a carry-propagate output of the adder bit slice;
a carry circuit having a carry-generate input coupled to the first circuit node of the logic circuit, a carry-propagate input coupled to the second circuit node of the logic circuit, a carry-generate output, and a carry-propagate output, the carry circuit being programmable to selectively pass one of the carry-generate input and a fixed logic value to the carry-generate output, and to pass one of the carry-propagate input and a fixed logic value to the carry-propagate output; and
a carry output circuit including a first input, a second input coupled to the carry-generate output of the carry circuit, a third input coupled to the carry-propagate output of the carry circuit, and an output.
2. The logic module of claim 1 wherein the logic circuit includes a first lookup table and a second lookup table.
3. The logic module of claim 1 wherein the carry circuit includes:
a first multiplexer having a first data input coupled to the first circuit node, and a second data input coupled to a first logic level, a programmable select input, and a carry-generate output; and
a second multiplexer having a first data input coupled to the second circuit node, a second data input coupled to a first logic level, a programmable select input, and a carry-propagate output.
4. The logic module of claim 3 , wherein:
the first multiplexer further includes a third data input coupled to a second logic level opposite to the first logic level and a second programmable select input; and
the second multiplexer further includes a third data input coupled to a second logic level opposite to the first logic level and a second programmable select input.
5. The logic module of claim 3 wherein the carry output circuit includes a carry-output multiplexer having a first data input coupled to the carry-generate output of the first multiplexer, a second data input, a select input coupled to the carry-propagate output of the second multiplexer, and an output.
6. The logic module of claim 2 , further including a data output multiplexer having a first data input coupled to an output of the first lookup table, a second data input coupled to an output of the second lookup table, a select input, and an output coupled to a data output node.
7. The logic module of claim 6 , further including a carry-select multiplexer having a first data input, a second data input coupled to the first input of the carry output circuit, a programmable select input, and an output coupled to the select input of the data output multiplexer.
8. A logic module section for a field programmable gate array including:
a section carry input;
a section carry output;
a plurality of logic modules, each logic module including:
a logic circuit programmable to implement an adder bit slice, the logic circuit including a logic function generator circuit, a first circuit node and a second circuit node, wherein the first circuit node is coupled to a carry-generate output of the adder bit slice and the second circuit node is coupled to a carry-propagate output of the adder bit slice,
a carry circuit having a carry-generate input coupled to the first circuit node of the logic circuit, a carry-propagate input coupled to the second circuit node of the logic circuit, a carry-generate output, and a carry-propagate output, the carry circuit being programmable to selectively pass one of the carry-generate input and a fixed logic value to the carry-generate output, and to pass one of the carry-propagate input and a fixed logic value to the carry-propagate output, and
a carry output circuit including a first input, a second input coupled to the carry-generate output of the carry circuit, a third input coupled to the carry-propagate output of the carry circuit, and an output;
wherein the carry output circuits of the plurality of logic modules are coupled in series with one another, wherein the first input of a first carry output circuit is coupled to the section carry input, the output of a last carry output circuit is coupled to the section carry output, and the input of each carry output circuit between the first and last carry output circuits is coupled to the output of an immediately preceding carry output circuit.
9. The logic module section of claim 8 , further including a section carry output multiplexer having a first data input coupled to the section carry input, a second data input coupled to the output of the last carry output circuit, a select input, and an output coupled to the section carry output.
10. The logic module section of claim 8 wherein each logic module further includes a data output multiplexer having a first data input coupled to an output of the first lookup table, a second data input coupled to an output of the second lookup table, a select input, and an output coupled to a data output node.
11. The logic module section of claim 10 , wherein each logic module further includes a carry-select multiplexer having a first data input, a second data input coupled to the first input of the carry output circuit, a programmable select input, and an output coupled to the select input of the data output multiplexer.
12. The logic module section of claim 8 , wherein the select input of the section carry output multiplexer is driven by selection circuitry.
13. The logic module section of claim 12 wherein the selection circuitry includes a first selection multiplexer having a first data input coupled to a first logic level, a second data input coupled to a second logic level opposite to the first logic level, a programmable select input, and an output coupled to the select input of the section carry output multiplexer.
14. The logic module section of claim 13 wherein the output of the first selection multiplexer is coupled to the select input of the section carry output multiplexer through a gate.
15. The logic module section of claim 14 further including a first propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a first one of the plurality of logic modules, and an output coupled to the gate.
16. The logic module section of claim 14 further including:
a first propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a first one of the plurality of logic modules, and an output coupled to the gate; and
a second propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a second one of the plurality of logic modules, and an output coupled to the gate.
17. The logic module section of claim 14 further including:
a first propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a first one of the plurality of logic modules, and an output coupled to the gate;
a second propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a second one of the plurality of logic modules, and an output coupled to the gate;
a third propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a third one of the plurality of logic modules, and an output coupled to the gate; and
a fourth propagation multiplexer having a first data input coupled to a first logic level, a second data input coupled to the carry-propagate output of a fourth one of the plurality of logic modules, and an output coupled to the gate.
18. A logic module for a field programmable gate array integrated circuit device including:
a logic circuit programmable to implement an adder bit slice, the logic circuit including a logic function generator circuit, a first circuit node and a second circuit node, wherein the first circuit node is coupled to a carry-generate output of the adder bit slice and the second circuit node is coupled to a carry-propagate output of the adder bit slice;
a carry circuit having a carry-generate input coupled to the first circuit node of the logic circuit, a carry-propagate input coupled to the second circuit node of the logic circuit, a carry-generate output, and a carry-propagate output, the carry circuit including programmable means for selectively passing one of the carry-generate input and a fixed logic value to the carry-generate output, and for selectively passing one of the carry-propagate input and a fixed logic value to the carry-propagate output; and
a carry output circuit including a first input, a second input coupled to the carry-generate output of the carry circuit, a third input coupled to the carry-propagate output of the carry circuit, and an output.
19. A logic module section for a field programmable gate array including:
a section carry input;
a section carry output;
a plurality of logic modules, each logic module including:
a logic circuit programmable to implement an adder bit slice, the logic circuit including a logic function generator circuit, a first circuit node and a second circuit node, wherein the first circuit node is coupled to a carry-generate output of the adder bit slice and the second circuit node is coupled to a carry-propagate output of the adder bit slice,
a carry circuit having a carry-generate input coupled to the first circuit node of the logic circuit, a carry-propagate input coupled to the second circuit node of the logic circuit, a carry-generate output, and a carry-propagate output, the carry circuit including programmable means for selecting any of the plurality of logic modules to operate as a least significant bit of the adder bit slice, and
a carry output circuit including a first input, a second input coupled to the carry-generate output of the carry circuit, a third input coupled to the carry-propagate output of the carry circuit, and an output;
wherein the carry output circuits of the plurality of logic modules are coupled in series with one another, wherein the first input of a first carry output circuit is coupled to the section carry input, the output of a last carry output circuit is coupled to the section carry output, and the input of each carry output circuit between the first and last carry output circuits is coupled to the output of an immediately preceding carry output circuit.