Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
View Patent ↗A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer containing a plurality of semiconductor die each having an optically active region;
forming a passivation layer over an entire surface of the semiconductor wafer, the passivation layer having a clear portion for passage of light to the optically active region of the semiconductor die;
mounting a glass wafer over an entire surface of the passivation layer;
singulating the semiconductor wafer into individual semiconductor die each with a portion of the glass wafer and clear portion of the passivation layer;
mounting the semiconductor die to a carrier with separation between the semiconductor die;
depositing encapsulant over the carrier within the separation to form an expansion region around a periphery of the semiconductor die;
forming a first via through the expansion region, glass wafer, and passivation layer;
forming a second via through the glass wafer and passivation layer to a contact pad on the semiconductor die; and
filling the first and second vias with conductive material.
2. The method of claim 1 , further including:
forming a conductive layer between the conductive material in the first and second vias; and
forming an interconnect structure over the conductive layer.
3. The method of claim 1 , further including:
forming a conductive layer over a surface of the semiconductor die opposite the optically active region, the conductive layer being electrically connected to the conductive material in the first via; and
forming an interconnect structure over the conductive layer.
4. The method of claim 1 , further including forming the passivation layer by printing, lamination, or spin coating.
5. The method of claim 1 , wherein forming the expansion region includes:
forming an enclosure around the semiconductor die while mounted to the carrier; and
filling the enclosure with the encapsulant.
6. A method of making a semiconductor device, comprising:
providing a semiconductor wafer containing a plurality of semiconductor die each having an optically active region;
forming a passivation layer over an entire surface of the semiconductor wafer, the passivation layer having a clear portion for passage of light to the optically active region of the semiconductor die;
mounting a glass wafer over an entire surface of the passivation layer;
singulating the semiconductor wafer into individual semiconductor die each with a portion of the glass wafer and clear portion of the passivation layer;
forming a first conductive via through the glass wafer and passivation layer to a contact pad on the semiconductor die;
mounting the semiconductor die to a carrier with separation between the semiconductor die; and
depositing encapsulant over the carrier within the separation to form an expansion region around the semiconductor die.
7. The method of claim 6 , further including:
forming a second conductive via through the expansion region, glass wafer, and passivation layer;
forming a conductive layer between the first conductive via and second conductive via; and
forming an interconnect structure over the conductive layer.
8. The method of claim 6 , wherein forming the expansion region includes:
forming an enclosure around the semiconductor die while mounted to the carrier; and
filling the enclosure with the encapsulant.
9. The method of claim 6 , further including forming a second conductive via through the semiconductor die, the second conductive via being electrically connected to the first conductive via.
10. The method of claim 9 , further including:
forming a conductive layer over a surface of the semiconductor die opposite the optically active region, the conductive layer being electrically connected to the second conductive via; and
forming an interconnect structure over the conductive layer.
11. A method of making a semiconductor device, comprising:
providing a semiconductor wafer containing a plurality of semiconductor die each having an optically active region;
forming a passivation layer over the semiconductor wafer, the passivation layer having a clear portion for passage of light to the optically active region of the semiconductor die;
singulating the semiconductor wafer into individual semiconductor die;
mounting the semiconductor die to a carrier with separation between the semiconductor die;
depositing encapsulant over the carrier within the separation to form an expansion region around the semiconductor die; and
forming a first conductive via through the expansion region.
12. The method of claim 11 , further including mounting a glass wafer over the passivation layer prior to singulation of the semiconductor wafer.
13. The method of claim 11 , further including mounting a glass die over the clear portion of the passivation layer.
14. The method of claim 11 , further including forming a conductive layer over a surface of the semiconductor die common with the optically active region, the conductive layer being electrically connected to the first conductive via.
15. The method of claim 14 , further including forming an interconnect structure over the conductive layer.
16. The method of claim 11 , wherein the first conductive via extends through the passivation layer.
17. The method of claim 11 , further including:
forming a conductive layer over a surface of the semiconductor die opposite the optically active region, the conductive layer being electrically connected to the first conductive via; and
forming an interconnect structure over the conductive layer.
18. The method of claim 11 , further including forming a second conductive via through the passivation layer to the semiconductor die.