Monolithically integrated multiplexer-translator-demultiplexer circuit and method
View Patent ↗A monolithically integrated multiplexer-translator-demultiplexer and a method for multiplexing and translating an electrical signal or demultiplexing and translating an electrical signal. A multiplexer and a demultiplexer are monolithically integrated with a translator. Circuits that operate at different voltage supply levels from each other may be coupled to the multiplexer and a circuit that operates at a different voltage supply level from the circuits coupled to the multiplexer or that operates at the same voltage supply level as at least one of the circuits coupled to the multiplexer is coupled to the demultiplexer. The monolithically integrated multiplexer-translator-demultiplexer selects a signal from one of the circuits coupled to the multiplexer, translates its voltage level and provides the translated signal level as an output signal. Alternatively, the monolithically integrated multiplexer-translator-demultiplexer creates demultiplexed signals from an electrical signal and translates the voltage levels of the demultiplexed signals.
1. A monolithically integrated multiplexer-translator-demultiplexer, comprising:
a first bidirectional data transmission stage having a first node, a second node, and a third node, the third node coupled for receiving a first source of operating potential;
a second bidirectional data transmission stage having a first node, a second node, and a third node, the first node of the second bidirectional data transmission stage coupled to the second node of the first bidirectional data transmission stage, the second node of the second bidirectional data transmission stage coupled to the first node of the first bidirectional data transmission stage, and the third node of the second bidirectional data transmission stage coupled for receiving a second source of operating potential;
a third bidirectional data transmission stage having a first node, a second node, and a third node, the second node of the third bidirectional data transmission stage coupled to the first node of the second bidirectional data transmission stage and the third node of the third bidirectional data transmission stage coupled for receiving a third source of operating potential; and
a fourth bidirectional data transmission stage having a first node, a second node, and a third node, the first node of the fourth bidirectional data transmission stage coupled to the second node of the third bidirectional data transmission stage, the second node of the fourth bidirectional data transmission stage coupled to the first node of the third bidirectional data transmission stage and the third node of the fourth bidirectional data transmission stage coupled for receiving the second source of operating potential.
2. The monolithically integrated multiplexer-translator-demultiplexer of claim 1 , wherein the first bidirectional data transmission stage comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of operating potential, the first current carrying electrode serving as the first node of the first bidirectional data transmission stage and the second current carrying electrode serving as the second node of the first bidirectional data transmission stage;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the first source of operating potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor; and
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor.
3. The monolithically integrated multiplexer-translator-demultiplexer of claim 2 , wherein the second bidirectional data transmission stage comprises:
a third transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the third transistor serving as the third node of the second bidirectional data transmission stage and the second current carrying electrode of the third transistor serving as the second node of the second bidirectional data transmission stage;
a second one-shot coupled between the first node of the first bidirectional data transmission stage and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.
4. The monolithically integrated multiplexer-translator-demultiplexer of claim 3 , wherein the third bidirectional data transmission stage comprises:
a fourth transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the third source of operating potential, the first current carrying electrode serving as the first node of the third bidirectional data transmission stage and the second current carrying electrode serving as the second node of the third bidirectional data transmission stage;
a fifth transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the fifth transistor coupled for receiving the first source of operating potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the fourth transistor;
a third one-shot coupled between the second current carrying electrode of the fourth transistor and the control electrode of the fifth transistor; and
a third resistor coupled from the first current carrying electrode of the fourth transistor to the second current carrying electrode of the fifth transistor.
5. The monolithically integrated multiplexer-translator-demultiplexer of claim 4 , wherein the fourth bidirectional data transmission stage comprises:
a sixth transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode of the sixth transistor serving as the third node of the fourth bidirectional data transmission stage and the second current carrying electrode of the sixth transistor serving as the second node of the fourth bidirectional data transmission stage;
a fourth one-shot coupled between the first current carrying electrode of the fourth transistor and the control electrode of the sixth transistor; and
a fourth resistor coupled from the first current carrying electrode of the sixth transistor to the second current carrying electrode of the sixth transistor.
6. The monolithically integrated multiplexer-translator-demultiplexer of claim 1 , further including a selector that selects at least one bidirectional data transmission stage from the first, second, third, and fourth bidirectional data transmission stages.
7. The monolithically integrated multiplexer-translator-demultiplexer of claim 1 , further including first and second transceiver circuits coupled to the first and third bidirectional data transmission stages, respectively.
8. The monolithically integrated multiplexer-translator-demultiplexer of claim 7 , further including a third transceiver circuit coupled to the second node of the second bidirectional data transmission stage.
9. The monolithically integrated multiplexer-translator-demultiplexer of claim 1 , further including a central processing unit coupled to the second bidirectional data transmission stage and at least two SDIO systems coupled to the first bidirectional data transmission stage.
10. A monolithically integrated multiplexer-translator-demultiplexer, comprising:
a first conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a first source of potential, a second input of the at least two inputs serves as a first input/output node, a first output of the at least two outputs is coupled for receiving a second source of potential and a second output of the at least two outputs serves as a second input/output node; and
a second conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a third source of potential, a second input of the at least two inputs serves as a third input/output node, a first output of the at least two outputs is coupled to the first output of the at least two outputs of the first conduction channel and a second output of the at least two outputs is coupled to the second output of the at least two outputs of the first conduction channel.
11. The monolithically integrated multiplexer-translator-demultiplexer of claim 10 , wherein the first conduction channel comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of potential, the first current carrying electrode serving as the first input/output node of the first conduction channel and the second current carrying electrode serving as the second input/output node of the first conduction channel;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the first source of potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor;
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor,
a third transistor having a control electrode and first and second current carrying electrodes, the first electrode of the third transistor serving as the third node of the second conduction channel and the second electrode of the third transistor serving as the second input/output node of the second conduction channel;
a second one-shot coupled between the first node of the first conduction channel and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.
12. The monolithically integrated multiplexer-translator-demultiplexer of claim 11 , wherein the second conduction channel comprises:
a fourth transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the second source of potential, the first current carrying electrode serving as the third input/output node of the second conduction channel and the second current carrying electrode serving as the fourth input/output node of the second conduction channel;
a fifth transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the fifth transistor coupled for receiving the second source of potential and the second current carrying electrode of the fifth transistor coupled to the first current carrying electrode of the fourth transistor;
a third one-shot coupled between the second current carrying electrode of the fourth transistor and the control electrode of the fifth transistor;
a third resistor coupled from the first current carrying electrode of the fifth transistor to the second current carrying electrode of the fifth transistor;
a sixth transistor having a control electrode and first and second current carrying electrodes, the first electrode of the sixth transistor serving as the third input/output node of the second conduction channel and the second electrode of the sixth transistor serving as the second input/output node of the second conduction channel;
a fourth one-shot coupled between the first node of the second conduction channel and the control electrode of the sixth transistor; and
a fourth resistor coupled from the first current carrying electrode of the sixth transistor to the second current carrying electrode of the sixth transistor.
13. The monolithically integrated multiplexer-translator-demultiplexer of claim 10 , further including:
a third conduction channel having at least two inputs and at least two outputs, wherein a first input of the at least two inputs is coupled for receiving a fourth source of potential, a second input of the at least two inputs serves as a fourth input/output node, a first output of the at least two outputs is coupled to the first output of the at least two outputs of the first conduction channel and a second output of the at least two outputs is coupled to the second output of the at least two outputs of the first conduction channel.
14. The monolithically integrated multiplexer-translator-demultiplexer of claim 13 , wherein the third conduction channel comprises:
a first transistor having first and second current carrying electrodes and a control electrode, the control electrode coupled for receiving the first source of potential, the first current carrying electrode serving as the fourth input/output node of the third conduction channel and the second current carrying electrode coupled to the second input/output node of the first conduction channel;
a second transistor having first and second current carrying electrodes and a control electrode, the first current carrying electrode of the second transistor coupled for receiving the fourth source of potential and the second current carrying electrode of the second transistor coupled to the first current carrying electrode of the first transistor;
a first one-shot coupled between the second current carrying electrode of the first transistor and the control electrode of the second transistor,
a first resistor coupled from the first current carrying electrode of the second transistor to the second current carrying electrode of the second transistor;
a third transistor having a control electrode and first and second current carrying electrodes, the first electrode of the third transistor coupled to the third node of the second conduction channel and the second electrode of the third transistor serving as the second input/output node of the first conduction channel;
a second one-shot coupled between the first node of the third conduction channel and the control electrode of the third transistor; and
a second resistor coupled from the first current carrying electrode of the third transistor to the second current carrying electrode of the third transistor.
15. A method for one of multiplexing and leveling shifting a first electrical signal or level shifting and demultiplexing a second electrical signal, comprising:
multiplexing and level shifting the electrical signal by:
providing a plurality of electrical signals to a monolithically integrated circuit;
using the monolithically integrated circuit to select the first electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected first electrical signal to form a level shifted first electrical signal; or
demultiplexing the second electrical signal by:
providing a second electrical signal to the monolithically integrated circuit;
using the monolithically integrated circuit to adjust the signal level of the second electrical signal to form a level shifted second electrical signal; and
transmitting the level shifted second electrical signal to a plurality of input/output nodes.
16. The method of claim 15 , wherein providing the second electrical signal includes providing the second electrical signal from a central processing unit.
17. The method of claim 15 , wherein providing the plurality of electrical signals to the monolithically integrated circuit includes providing a plurality of electrical signals as a plurality of voltage signals.
18. A method for multiplexing and level shifting electrical signals, comprising:
providing a plurality of electrical signals to a monolithically integrated circuit, wherein the monolithically integrated circuit comprises a plurality of conduction channels and wherein each electrical signal of the plurality of electrical signals corresponds to a conduction channel of the plurality of conduction channels and wherein one or more of the conduction channels of the plurality of conduction channels is capable of transmitting an electrical signal in first and second directions, the second direction opposite that of the first direction;
using the monolithically integrated circuit to select an electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected electrical signal to form a level shifted selected electrical signal, wherein adjusting the signal level of the selected electrical signal includes increasing the electrical signal.
19. The method of claim 18 , wherein the electrical signal is a voltage signal.
20. A method for multiplexing and level shifting electrical signals, comprising:
providing a plurality of electrical signals to a monolithically integrated circuit, wherein the monolithically integrated circuit comprises a plurality of conduction channels and wherein each electrical signal of the plurality of electrical signals corresponds to a conduction channel of the plurality of conduction channels and wherein one or more of the conduction channels of the plurality of conduction channels is capable of transmitting an electrical signal in first and second directions, the second direction opposite that of the first direction;
using the monolithically integrated circuit to select an electrical signal of the plurality of electrical signals; and
adjusting a signal level of the selected electrical signal to form a level shifted selected electrical signal, wherein adjusting the signal level of the selected electrical signal includes decreasing the electrical signal.