High-voltage dual-polarity I/O p-well pump ESD protection circuit
View Patent ↗An ESD protection circuit includes a discharge transistor formed in a p-well and having a drain coupled to the I/O pad, and a source coupled to ground. A MOS capacitor has a gate coupled to the I/O pad. A first resistor is coupled between the source and drain of the MOS capacitor and ground. A pulldown transistor has a drain coupled to the source and drain of the MOS capacitor, a source coupled to ground, and a gate coupled to a power-supply voltage node. A p-well control transistor has a source coupled to ground, and a drain coupled to the p-well. A second resistor is coupled between the I/O pad and the drain of the p-well control transistor. A pump transistor has a gate coupled to the gate of the discharge transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.
1. A high-voltage dual-polarity p-well pump ESD protection circuit for an I/O pad of an integrated circuit comprising:
an n-channel MOS discharge transistor formed in a p-well and having a drain coupled to the I/O pad, a source coupled to ground, and a gate;
a MOS capacitor having a gate coupled to the I/O pad, a source and a drain;
a first resistor coupled between the source and drain of the MOS capacitor and a ground node;
an n-channel MOS pulldown transistor having a drain coupled to the source and drain of the MOS capacitor, a source coupled to the ground node, and a gate coupled to a power-supply voltage node;
an n-channel MOS p-well control transistor having a source coupled to the ground node, a drain coupled to the p-well, and a gate;
a second resistor coupled between the I/O pad and the drain of the n-channel MOS p-well control transistor;
an n-channel MOS pump transistor having a gate coupled to the gate of the first n-channel MOS transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.
2. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 wherein the first resistor and the MOS capacitor have a time constant of about 10 ns.
3. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 2 wherein the first resistor has a resistance of about 15K ohms.
4. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 wherein the n-channel MOS p-well control transistor has a time constant between about 600 ns and about 800 ns.
5. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 4 wherein the second resistor has a resistance of about 15K ohms.
6. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 where the n-channel MOS discharge transistor is formed in a p-well surrounded by a guard ring.
7. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 wherein the n-channel MOS discharge transistor, the MOS p-well control transistor, and the n-channel MOS pump transistor are formed in a common p-well surrounded by a guard ring.
8. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 7 wherein the n-channel MOS pulldown transistor is formed in the common p-well.
9. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 7 wherein the n-channel MOS pulldown transistor is formed in a p-well separate from the common p-well.
10. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 wherein the n-channel MOS discharge transistor is a multifinger structure.
11. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 1 wherein the n-channel MOS discharge transistor and the n-channel MOS pump transistor are multifinger structures.
12. The high-voltage dual-polarity p-well pump ESD protection circuit of claim 11 wherein the n-channel MOS pulldown transistor and the n-channel MOS p-well control transistors are multifinger structures.