Low overhead memory management system and method
View Patent ↗A block of contiguous data storage locations of a memory is divided into pools of memory chunks. The memory chunks in same ones of the pools have equal chunk sizes. The memory chunks in different ones of the pools have different chunk sizes. In each of the pools, the memory chunks are addressable by respective chunk base physical addresses in a respective linear contiguous sequence that starts from a respective pool base physical address. The physical addresses of the memory chunks are translated into corresponding internal handles and vice versa, where each of the internal handles is smaller in size than its corresponding physical address. For each of the pools, an associated pool queue comprising respective ones of the internal handles to allocatable ones of the memory chunks in the pool is maintained.
1. A machine-implemented memory management method, comprising:
dividing a block of contiguous data storage locations of a memory into pools of memory chunks, wherein the memory chunks in same ones of the pools have equal chunk sizes, the memory chunks in different ones of the pools have different chunk sizes, and in each of the pools the memory chunks are addressable by respective chunk base physical addresses in a respective linear contiguous sequence that starts from a respective pool base physical address;
translating between the physical addresses of the memory chunks and corresponding internal handles, wherein each of the internal handles is smaller in size than its corresponding physical address; and
for each of the pools, maintaining an associated pool queue comprising respective ones of the internal handles to allocatable ones of the memory chunks in the pool.
2. The method of claim 1 , wherein the linear contiguous sequences of physical addresses collectively form a linear, sequential, and contiguous physical address space.
3. The method of claim 1 , wherein the dividing comprises:
receiving addressing and structural parameter values specifying the division of the block of the contiguous data storage locations into the pools;
determining the respective physical addresses of the memory chunks from the received parameter values;
determining respective ones of the internal handles from the determined physical addresses; and
loading the respective pool queues with the determined internal handles.
4. The method of claim 3 , wherein the translating comprises calculating the internal handles from the corresponding ones of the physical addresses based on the received addressing and structural parameter values.
5. The method of claim 1 , wherein the translating comprises extracting a respective segment from each of the physical addresses to obtain the corresponding internal handle.
6. The method of claim 1 , wherein the translating comprises concatenating one or more respective address segments to each of the internal handles to obtain the corresponding physical address.
7. The method of claim 1 , further comprising in response to receipt of a specified memory size along with a command to allocate memory:
identifying one of the pools of memory chunks having a chunk size at least as large as the specified memory size;
removing a selected one of the internal handles from the pool queue associated with the identified pool;
translating the selected internal handle into one of the physical addresses; and
returning the physical address translated from the selected internal handle.
8. The method of claim 1 , further comprising in response to receipt of a specified physical address along with a command to de-allocate memory:
determining the respective chunk base physical address of the memory chunks that comprises the data storage location that is addressed by the specified physical address;
translating the determined chunk base physical address into a respective one of the internal handles; and
loading the respective internal handle translated from the determined chunk base physical address into the pool queue associated with the pool comprising the identified memory chunk.
9. The method of claim 8 , wherein the determining comprises selecting the one of the chunk base physical addresses that is nearest without exceeding the specified physical address as the determined chunk base physical address.
10. Apparatus, comprising:
a memory;
a processing unit operable to perform operations comprising
dividing a block of contiguous data storage locations of the memory into pools of memory chunks, wherein the memory chunks in same ones of the pools have equal chunk sizes, the memory chunks in different ones of the pools have different chunk sizes, and in each of the pools the memory chunks are addressable by respective chunk base physical addresses in a respective linear contiguous sequence that starts from a respective pool base physical address; and
a memory manager operable to perform operations comprising
translating between the physical addresses of the memory chunks and corresponding internal handles, wherein each of the internal handles is smaller in size than its corresponding physical address, and
for each of the pools, maintaining an associated pool queue comprising respective ones of the internal handles to allocatable ones of the memory chunks in the pool.
11. The apparatus of claim 10 , wherein the linear contiguous sequences of physical addresses collectively form a linear, sequential, and contiguous physical address space.
12. The apparatus of claim 10 , wherein:
in the dividing the processing unit is operable to receive addressing and structural parameter values specifying the division of the block of the contiguous data storage locations into the pools, and determine the respective physical addresses of the memory chunks from the received parameter values; and
in the translating, the memory manager is operable to determine respective ones of the internal handles from the determined physical addresses, and load the respective pool queues with the determined internal handles.
13. The apparatus of claim 12 , wherein in the translating the memory manager is operable to calculate the internal handles from the corresponding ones of the physical addresses based on the received addressing and structural parameter values.
14. The apparatus of claim 10 , wherein in the translating the memory manager is operable to extract a respective segment from each of the physical addresses to obtain the corresponding internal handle.
15. The apparatus of claim 10 , wherein in the translating the memory manager is operable to concatenate one or more respective address segments to each of the internal handles to obtain the corresponding physical address.
16. The apparatus of claim 10 , wherein, in response to receipt of a specified memory size along with a command to allocate memory, the memory manager is operable to perform operations comprising:
identifying one of the pools of memory chunks having a chunk size at least as large as the specified memory size;
removing a selected one of the internal handles from the pool queue associated with the identified pool;
translating the selected internal handle into one of the physical addresses; and
returning the physical address translated from the selected internal handle.
17. The apparatus of claim 10 , wherein, in response to receipt of a specified physical address along with a command to de-allocate memory, the memory manager is operable to perform operations comprising:
determining the respective chunk base physical address of the memory chunks that comprises the data storage location that is addressed by the specified physical address;
translating the determined chunk base physical address into a respective one of the internal handles; and
loading the respective internal handle translated from the determined chunk base physical address into the pool queue associated with the pool comprising the identified memory chunk.
18. The apparatus of claim 17 , wherein in the determining the memory manager is operable to select the one of the chunk base physical addresses that is nearest without exceeding the specified physical address as the determined chunk base physical address.
19. The apparatus of claim 10 , further comprising a wireless transceiver operable to transmit and receive packets of data.
20. The apparatus of claim 10 , wherein the physical addresses are defined with respect to a bounded physical address space, and the memory manager performs the translating with respect to physical addresses within a first portion of physical address space; and further comprising one or more additional memory mangers operable to perform the translating with respect to physical addresses with different respective portions of the physical address space, wherein the portions of the physical address space are non-overlapping and collectively span the physical address space in its entirety.