Conditioning input buffer for clock interpolation
View Patent ↗A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.
1. A conditioning buffer circuit, comprising:
a first buffer that receives a first input signal; and
a second buffer, coupled to the first buffer, that receives a second input signal, wherein:
the first input signal has a first delay and the second input signal has a second delay different from the first delay,
the first input signal and the second input signal are signals obtained from a set of mutually delayed signals, and
the conditioning buffer circuit outputs a conditioned output signal based on a combination of a first output of the first buffer and a second output of the second buffer, wherein:
the second buffer has a weaker drive strength than the first buffer,
the drive strength of the second buffer is fixed, and
the first buffer is a variable strength buffer circuit having a variable drive strength.
2. The circuit of claim 1 , wherein the first buffer and the second buffer are coupled to form an interpolator, having weights proportional to respective drive strengths of the first and second buffers, which operates as a two-tap transversal filter.
3. The circuit of claim 1 , wherein the set of mutually delayed signals is a set of mutually delayed clock signals.
4. The circuit of claim 3 , wherein the set of mutually delayed clock signals is a set of equidistant N clock signals having a phase difference of 360/N degrees.
5. The circuit of claim 3 , wherein the conditioning buffer circuit outputs the conditioned output signal to a clock phase interpolator circuit.
6. The circuit of claim 5 , wherein the set of mutually delayed clock signals comprises a first clock signal having a phase of 0 degrees, a second clock signal having a phase of 90 degrees, a third clock signal having a phase of 180 degrees, and a fourth clock signal having a phase of 270 degrees.
7. The circuit of claim 1 , wherein the conditioning buffer circuit is integrated in an integrated circuit device.
8. The circuit of claim 7 , wherein the integrated circuit device is part of an electronic product having one or more integrated circuit devices.
9. A clock phase interpolator circuit, comprising:
at least one clock generator circuit;
at least one clock conditioning buffer circuit coupled to the at least one clock generator circuit; and
a clock phase interpolator coupled to the at least one clock conditioning buffer circuit, wherein each clock conditioning buffer circuit of the at least one clock conditioning buffer circuit comprises:
a first buffer that receives a first clock input signal; and
a second buffer, coupled to the first buffer, that receives a second clock input signal, wherein:
the first clock input signal has a first phase delay and the second clock input signal has a second phase delay different from the first phase delay,
the first clock input signal and the second clock input signal are clock signals obtained from a set of clock signals having different phase delays generated by the at least one clock generator circuit,
the conditioning buffer circuit outputs a conditioned clock output signal to the clock phase interpolator based on a combination of a first output of the first buffer and a second output of the second buffer,
the second buffer has a weaker drive strength than the first buffer,
the drive strength of the second buffer is fixed, and
the first buffer is a variable strength buffer circuit having a variable drive strength.
10. The clock phase interpolator circuit of claim 9 , wherein conditioned output signals of two clock conditioning buffer circuits of the at least one clock conditioning buffer circuit have substantially overlapped edges.
11. A clock phase interpolator circuit, comprising:
at least one clock generator circuit;
at least one clock conditioning buffer circuit coupled to the at least one clock generator circuit; and
a clock phase interpolator coupled to the at least one clock conditioning buffer circuit, wherein each clock conditioning buffer circuit of the at least one clock conditioning buffer circuit comprises:
a first buffer that receives a first clock input signal; and
a second buffer, coupled to the first buffer, that receives a second clock input signal, wherein:
the first clock input signal has a first phase delay and the second clock input signal has a second phase delay different from the first phase delay,
the first clock input signal and the second clock input signal are clock signals obtained from a set of clock signals having different phase delays generated by the at least one clock generator circuit,
the conditioning buffer circuit outputs a conditioned clock output signal to the clock phase interpolator based on a combination of a first output of the first buffer and a second output of the second buffer,
the first buffer and the second buffer are coupled to form an interpolator, having weights proportional to respective drive strengths of the first and second buffers, which operates as a two-tap transversal filter.
12. The clock phase interpolator circuit of claim 9 , wherein the set of clock signals having different phase delays generated by the at least one clock generator circuit comprises a set of equidistant N clock signals having a phase difference of 360/N degrees.
13. The clock phase interpolator circuit of claim 9 , wherein the clock phase interpolator circuit is integrated in an integrated circuit device.
14. The clock phase interpolator circuit of claim 13 , wherein the integrated circuit device is part of an electronic product having one or more integrated circuit devices.
15. The clock phase interpolator circuit of claim 9 , wherein the at least one clock conditioning buffer circuit comprises a plurality of clock conditioning buffer circuits coupled to the at least one clock generator circuit and the clock phase interpolator, and wherein, for each clock conditioning buffer circuit, the first clock input signal has a first phase delay that is at least 90 degrees out of phase from that of the second clock input signal.
16. The clock phase interpolator circuit of claim 15 , wherein the plurality of clock conditioning buffer circuits comprises:
a first clock conditioning buffer circuit having a first clock input signal with a 0 degree phase and a second clock input signal with a 90 degree phase;
a second clock conditioning buffer circuit having a first clock input signal with a 90 degree phase and a second clock input signal with a 180 degree phase;
a third clock conditioning buffer circuit having a first clock input signal with a 180 degree phase and a second clock input signal with a 270 degree phase; and
a fourth clock conditioning buffer circuit having a first clock input signal with a 270 degree phase and a second clock input signal with a 0 degree phase.
17. The clock phase interpolator circuit of claim 9 , wherein each clock conditioning buffer circuit in the at least one clock conditioning buffer circuit receives more than two clock input signals.
18. The clock phase interpolator circuit of claim 17 , wherein the more than two clock input signals comprises at least four clock input signals, each clock input signal having a phase that is at least 90 degrees out of phase from each other clock input signal.
19. The clock phase interpolator circuit of claim 17 , wherein the at least one clock conditioning buffer circuit comprises two clock conditioning buffer circuits, and wherein each clock conditioning buffer circuit receives the first clock input signal with a 0 degree phase, the second clock input signal with a 90 degree phase, a third clock input signal with a 180 degree phase, and a fourth clock input signal with a 270 degree phase.