Radiation tolerant SRAM bit
View Patent ↗In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
1. A field programmable gate array (FPGA) comprising:
a radiation tolerant static random access memory device comprising:
a first inverter having an input and an output;
a second inverter having an input and an output, said output of said first inverter coupled to said input of said second inverter and said output of said second inverter coupled to said input of said first inverter;
a resistor coupled between said first and second inverter; and
a pass transistor having a gate coupled to one of said first inverter output and said second inverter output,
wherein:
an RC time constant of the static random access memory device exceeds a selected recovery time of the static random access memory device; and
the pass transistor provides field programmability for the FPGA under control of the static random access memory device.
2. The FPGA in claim 1 wherein:
the resistor has a resistance of approximately 4 M ohms.
3. The FPGA in claim 1 wherein:
the selected recovery time is long enough to negate the effect of a high-energy particle impact on the static random access memory device.
4. The FPGA in claim 1 wherein the radiation tolerant static random access memory device further comprises:
a first write transistor coupled to said output of said first inverter and having a gate coupled to a source of write-control signals; and
a second write transistor coupled to said output of said second inverter and having a gate coupled to said source of write-control signals.
5. A field programmable gate array (FPGA) comprising:
a radiation tolerant static random access memory device comprising:
a first inverter having an input and an output;
a second inverter having an input and an output;
a first resistor coupled between said output of said first inverter and said input of said second inverter;
a second resistor coupled between said output of said second inverter and said input of said first inverter;
a first write transistor coupled to said output of said first inverter and having a gate coupled to a source of write-control signals;
a second write transistor coupled to said output of said second inverter and having a gate coupled to said source of write-control signals; and
a pass transistor having a gate coupled to said output of one of said first and second inverters.
6. A field programmable gate array (FPGA) according to claim 5 wherein:
said first and second inverters comprise a plurality of pass transistors.
7. In a field programmable gate array (FPGA), a method of producing a radiation tolerant static random access memory device comprising:
providing a first inverter having an input and an output;
coupling a second inverter having an input and an output to said output of said first inverter to said input of said second inverter and coupling said output of said second inverter to said input of said first inverter;
coupling a resistor between said first and second inverter;
coupling a pass transistor gate to one of said first inverter output and said second inverter output;
coupling a first write transistor to said output of said first inverter and coupling a gate to a source of write-control signals; and
coupling a second write transistor to said output of said second inverter and coupling a gate to said source of write-control signals.
8. In a field programmable gate array (FPGA), a method of producing a radiation tolerant static random access memory device comprising:
providing a first inverter having an input and an output;
providing a second inverter having an input and an output;
coupling a first resistor between said output of said first inverter and said input of said second inverter;
coupling a second resistor between said output of said second inverter and said input of said first inverter;
coupling a first write transistor coupled to said output of said first inverter and coupling a gate of said first write transistor to a source of write-control signals;
coupling a second write transistor coupled to said output of said second inverter and coupling a gate of said second write transistor to said source of write-control signals; and
coupling a pass transistor having a gate to one of said first inverter output and said second inverter output.
9. A method of producing a radiation tolerant field programmable gate array (FPGA) according to claim 8 wherein:
said first and second inverters comprise a plurality of pass transistors.