IP Library Granted Patent US 7,710,303
Granted Patent B2
US 7,710,303 · App. 12/051,170 · Granted May 4, 2010

Analog-to-digital converter offset and gain calibration using internal voltage references

Assignee: Microchip Technology Incorporated
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Quick Facts
Patent No.
US 7,710,303
App. No.
12/051,170
Granted
May 4, 2010
Kind
B2
Abstract

A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values.

Claims (41)

1. A mixed signal device having an analog-to-digital converter that is calibrated using internal voltage references, comprising:

a digital processor;

an analog-to-digital converter (ADC);

an analog multiplexer;

a voltage divider connected to a power supply voltage and deriving a plurality of different voltage values from the power supply voltage and supplying two of the plurality of different voltages, Y 1 and Y 2 , to two inputs of the analog multiplexer;

the ADC is connected to an output of the analog multiplexer and to the digital processor, and

the ADC converts the two of the plurality of different voltage values, Y 1 and Y 2 , to digital voltage values, X 1 and X 2 , respectively, and sends the digital voltage values, X 1 and X 2 , to the digital processor;

wherein the digital processor calculates gain, m, and offset, c, values required for calibrating the ADC output by using the two of the plurality of different voltage values, Y 1 and Y 2 , as voltage reference points to solve for m and c in equations: Y 1 =m*X 1 +c and Y 2 =m*X 2 +c.

2. The mixed signal device according to claim 1 , further comprising a voltage reference connected to another input of the analog multiplexer, wherein the digital processor further refines the calculation of the gain, m, and offset, c, values required for calibrating the ADC output to an absolute voltage value from the voltage reference.

3. The mixed signal device according to claim 2 , wherein the voltage reference is a Bandgap voltage reference and the absolute voltage value is about 1.2 volts.

4. The mixed signal device according to claim 1 , wherein the two of the plurality of different voltage values, Y 1 and Y 2 , are approximately one-quarter and three-quarters of the power supply voltage, respectively.

5. The mixed signal device according to claim 1 , wherein the ADC output is calibrated by adjusting the ADC analog circuit parameters with the calculated gain, m, and offset, c, values.

6. The mixed signal device according to claim 1 , wherein the analog multiplexer couples external voltages to the ADC for conversion to digital values that are read by the digital processor.

7. The mixed signal device according to claim 6 , wherein the ADC output is calibrated with al processor by adjusting the digital values from the ADC using the calculated gain, m, and offset, c, values.

8. A mixed signal device having an analog-to-digital converter that is calibrated using internal voltage references, comprising:

a digital processor;

an analog-to-digital converter (ADC);

an analog multiplexer;

a voltage reference suppling at least two different voltages, Y 1 and Y 2 , to at least two inputs, respectively, of the analog multiplexer;

the ADC is connected to an output of the analog multiplexer and to the digital processor; and

the ADC converts the at least two different voltage values, Y 1 and Y 2 , to digital voltage values, X 1 and X 2 , respectively, and sends the digital voltage values, X 1 and X 2 , to the digital processor;

wherein the digital processor calculates gain, m, and offsets values required for calibrating the ADC output by using the at least two different voltages, Y 1 and Y 2 , from the voltage reference as voltage reference points to solve for m and c in equations: Y 1 =m*X 1 +c and Y 2 =m*X 2 +c.

9. The mixed signal device according to claim 8 , wherein the voltage reference is a Bandgap voltage reference and the at least two different voltages, Y 1 and Y 2 , are about 0.6 volts and about 1.2 volts, respectively.

10. The mixed signal device according to claim 8 , wherein the at least two different voltages, Y 1 and Y 2 , from the voltage reference are approximately one-quarter and three-quarters of the voltage reference, respectively.

11. The mixed signal device according to claim 8 , wherein the ADC output is calibrated by adjusting the ADC analog circuit parameters with the calculated gain, m, and offset, c, values.

12. The mixed signal device according to claim 8 , wherein the analog multiplexer couples external voltages to the ADC for conversion to digital values that are read by the digital processor.

13. The mixed signal device according to claim 12 , wherein the ADC output is calibrated with the digital processor by adjusting the digital values from the ADC using the calculated gain, m, and offset, c, values.

14. A method for calculating gain and offset necessary to calibrate an analog-to-digital converter by using internal reference voltages, said method comprising the steps of:

receiving an analog first reference voltage, Y 1 , at an input of an analog-to-digital converter (ADC);

converting the analog first reference voltage, Y 1 , to a digital first voltage value, X 1 , with the ADC;

receiving an analog second reference voltage, Y 1 , at the input of the ADC;

converting the analog second reference voltage, Y 2 , to a digital second voltage value, X 2 , with the ADC;

calculating gain, m, and offset, c, values by solving for m and c in equations: Y 1 =m*X 1 +c and Y 2 =m*X 2 +c; and

calibrating the ADC with the calculated gain, m, and offset, c, values so that the first and second voltage values, X 1 and X 2 , substantially match in values the first and second reference voltages, Y 1 and Y 2 .

15. The method according to claim 14 , wherein the first reference voltage, Y 1 , is about one-quarter of a power supply voltage.

16. The method according to claim 14 , wherein the second reference voltage, Y 2 , is about three-quarters of a power supply voltage.

17. The method according to claim 14 , wherein the first and second reference voltages, Y 1 and Y 2 , are from a Bandgap voltage reference.

18. The method according to claim 17 , wherein the first reference voltage, Y 1 , is about 0.6 volts.

19. The method according to claim 17 , wherein the second reference voltage, Y 2 , is about 1.2 volts.

20. The method according to claim 14 , wherein the step of calibrating the ADC comprises the steps of adjusting the ADC analog circuit parameters with the calculated gain, m, and offset, c, values.

21. The method according to claim 14 , wherein the step of calibrating the ADC comprises the steps of correcting digital values from the ADC using the calculated gain, m, and offset, c, values.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2008
From: KAVAIYA, GAURANG
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 021268/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2008
From: KAVAIYA, GAURANG
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 020843/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2008
From: WOJEWODA, IGOR; PHOENIX, TIM
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 020672/0615 →
Continuity (2)
Provisional Application 6091222600 · Apr 17, 2007
Related Publication 20080278359A1 · Nov 13, 2008