IP Library Granted Patent US 7,901,987
Granted Patent B2
US 7,901,987 · App. 12/051,280 · Granted Mar 8, 2011

Package-on-package system with internal stacking module interposer

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,901,987
App. No.
12/051,280
Granted
Mar 8, 2011
Kind
B2
Abstract

A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.

Claims (58)

1. A method for manufacturing a package-on-package system comprising:

forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof;

forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof, and the first top electrical contacts extending entirely through and are exposed from an interposer encapsulant;

attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and

molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.

2. The method as claimed in claim 1 wherein forming the internal stacking module interposer comprises:

providing an interposer substrate;

attaching an integrated circuit die to the interposer substrate;

placing the first top electrical contacts on a top surface of the interposer substrate; and

molding the interposer encapsulant over the integrated circuit die and about to the top surface of the interposer substrate.

3. The method as claimed in claim 1 wherein attaching the internal stacking module interposer on the first integrated circuit package comprises:

inverting the internal stacking module interposer;

placing the internal stacking module interposer over the first integrated circuit package;

reflowing the first top electrical contacts of the internal stacking module interposer over the second top electrical contacts of the first integrated circuit package; and

molding the package encapsulant over the first integrated circuit package and around the internal stacking module interposer.

4. The method as claimed in claim 1 wherein attaching the stacked package comprises attaching the stacked package to a bottom surface of the internal stacking module interposer for electrical connection between second external electrical contacts and the base electrical connectors.

5. The method as claimed in claim 1 wherein molding the package encapsulant comprises surrounding the first integrated circuit package about to a first base carrier and partially surrounding the internal stacking module interposer with the package encapsulant.

6. A method for manufacturing a package-on-package system comprising:

forming an internal stacking module interposer having an interposer substrate, first top electrical contacts extending entirely through and are exposed from an interposer encapsulant, and an integrated circuit die;

providing a first integrated circuit package having a first base carrier with second top electrical contacts, a first integrated circuit die, side interconnections, and first external electrical contacts;

inverting the internal stacking module interposer;

attaching the internal stacking module interposer to the first integrated circuit package using the first top electrical contacts;

molding a package encapsulant over the first integrated circuit package and the internal stacking module interposer leaving a bottom surface of the interposer substrate exposed;

providing a stacked package having a second base carrier, a bottom integrated circuit die, a top integrated circuit die, second external electrical contacts, and a stacked package encapsulant; and

attaching the stacked package on the bottom surface of the internal stacking module interposer.

7. The method as claimed in claim 6 wherein forming the internal stacking module interposer comprises molding an interposer encapsulant over a top surface of the interposer substrate and leaving the first top electrical contacts partially exposed.

8. The method as claimed in claim 6 wherein attaching the internal stacking module interposer to the first integrated circuit package includes attaching the internal stacking module interposer to a logic device package or a flip chip integrated circuit package.

9. The method as claimed in claim 6 wherein attaching the stacked package to the internal stacking module interposer comprises:

placing the stacked package on the bottom surface of the internal stacking module interposer; and

attaching the stacked package to the internal stacking module interposer using the second external electrical contacts.

10. The method as claimed in claim 6 wherein molding the package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaves a package encapsulant cavity for attaching a stacked package over the internal stacking module interposer.

11. A package-on-package system comprising:

a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof, and the first top electrical contacts extending entirely through and are exposed from an interposer encapsulant;

an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof, the internal stacking module interposer attached to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and

a package encapsulant molded over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.

12. The system as claimed in claim 11 wherein forming the internal stacking module interposer comprises:

an interposer substrate, the first top electrical contacts on a top surface of the interposer substrate;

an integrated circuit die attached to the interposer substrate; and

wherein:

the interposer encapsulant is molded over the integrated circuit die and about to the top surface of the interposer substrate.

13. The system as claimed in claim 11 wherein the internal stacking module interposer attached on the first integrated circuit package comprises:

the internal stacking module interposer inverted over the first integrated circuit package;

the first top electrical contacts of the internal stacking module interposer reflowed over the second top electrical contacts of the first integrated circuit package; and

the package encapsulant molded over the first integrated circuit package and around the internal stacking module interposer.

14. The system as claimed in claim 11 wherein attaching the stacked package comprises attaching the stacked package to a bottom surface of the internal stacking module interposer for electrical connection between second external electrical contacts and the base electrical connectors.

15. The system as claimed in claim 11 wherein molding the package encapsulant comprises surrounding the first integrated circuit package about to a first base carrier and partially surrounding the internal stacking module interposer with the package encapsulant.

16. The system as claimed in claim 11 wherein:

the first integrated circuit package having a first base carrier with the second top electrical contacts, the first external electrical contacts, a first integrated circuit die, and side interconnections;

the internal stacking module interposer having an interposer substrate with first top electrical contacts, an integrated circuit die, and the interposer encapsulant;

the package encapsulant molded over the first integrated circuit package and the internal stacking module interposer leaving a bottom surface of the interposer substrate exposed; and

further comprising:

a stacked package having a second base carrier with a bottom integrated circuit die, a top integrated circuit die, second external electrical contacts, and a stacked package encapsulant, the stacked package attached on the bottom surface of the internal stacking module interposer.

17. The system as claimed in claim 16 wherein the internal stacking module interposer comprises the interposer encapsulant molded over a top surface of the interposer substrate and leaving the first top electrical contacts partially exposed.

18. The system as claimed in claim 16 wherein the internal stacking module interposer attached to the first integrated circuit package includes the internal stacking module interposer attached to a logic device package or a flip chip integrated circuit package.

19. The system as claimed in claim 16 wherein the stacked package attached to the internal stacking module interposer comprises:

the stacked package placed on the bottom surface of the internal stacking module interposer; and

the stacked package attached to the internal stacking module interposer using the second external electrical contacts.

20. The system as claimed in claim 16 wherein the package encapsulant attached over the first integrated circuit package and around the internal stacking module interposer leaves a package encapsulant cavity for a stacked package to be attached over the internal stacking module interposer.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2008
From: YANG, JOUNGIN; JUNG, DONGJIN
To: STATS CHIPPAC LTD.
Reel/Frame 020673/0979 →
Continuity (1)
Related Publication 20090236718A1 · Sep 24, 2009