Flip chip interconnection structure with bump on partial pad and method thereof
View Patent ↗A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.
1. A method of making a semiconductor package in a manufacturing process, comprising:
providing a semiconductor die with a plurality of solder bumps formed on bump pads;
providing a substrate having a plurality of contact pads each with an exposed sidewall;
disposing a solder resist opening over at least a portion of each contact pad; and
reflowing the solder bumps to metallurgically and electrically connect to the contact pads;
wherein each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad.
2. The method of claim 1 , wherein a value of X ranges from 5 to 20 microns.
3. The method of claim 1 , wherein the contact pad is equal in size to the solder resist opening.
4. The method of claim 1 , wherein the contact pad is smaller in size than the solder resist opening.
5. The method of claim 1 , wherein the contact pad is larger in size than the solder resist opening.
6. The method of claim 1 , wherein the solder bump substantially fills an area adjacent to the exposed sidewall of the contact pad.
7. The method of claim 1 , wherein a shape of the contact pad is selected from the group consisting of circular, rectangular, and donut-shaped.
8. A method of making a semiconductor device, comprising:
providing a substrate having a contact pad with an exposed sidewall; and
disposing a solder resist opening over at least a portion of the contact pad;
wherein the contact pad is sized such that the solder resist opening extends over the substrate by a maximum distance of X which is a function of a thickness of the exposed sidewall of the contact pad.
9. The method of claim 8 , wherein the contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of the thickness of the exposed sidewall of the contact pad.
10. The method of claim 8 , further including:
providing a semiconductor die with a solder bump formed on a bump pad; and
reflowing the solder bump to electrically connect to the contact pad.
11. The method of claim 8 , further including forming a solder bump through the solder resist opening over the contact pad.
12. The method of claim 8 , wherein a value of X ranges from 5 to 20 microns.
13. The method of claim 8 , wherein the contact pad is equal in size to the solder resist opening.
14. The method of claim 8 , wherein the contact pad is smaller or larger in size than the solder resist opening.
15. A method of interconnecting a semiconductor die to a substrate, comprising:
providing a semiconductor die with a solder bump formed on a bump pad;
providing a substrate having a contact pad with an exposed sidewall;
disposing a solder resist opening over at least a portion of the contact pad, the solder resist opening extending over a portion of the substrate by a maximum distance of X which is a function of a thickness of the exposed sidewall of the contact pad; and
reflowing the solder bump to electrically connect to the contact pad, the solder bump extending down the exposed sidewall of the contact pad.
16. The method of claim 15 , wherein the contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of the thickness of the exposed sidewall of the contact pad.
17. The method of claim 15 , wherein a value of X ranges from 5 to 20 microns.
18. The method of claim 15 , wherein the contact pad is equal in size to the solder resist opening.
19. The method of claim 15 , wherein the contact pad is smaller or larger in size than the solder resist opening.