Embedded cache memory in image sensors
View Patent ↗An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.
1. A memory cell comprising:
a first semiconductor region of a first doping type;
a second semiconductor region of a second doping type, the second doping type being different from the first doping type, the second semiconductor region being adjacent to the first semiconductor region;
a third semiconductor region of the first doping type adjacent to the second semiconductor region;
a fourth semiconductor region of the second doping type adjacent to the third semiconductor region; and
a gate extending into the third semiconductor region and having the first and second semiconductor regions on a first side of the gate, having the fourth semiconductor region on a second side of the gate, and having the third semiconductor region on the remaining portions of the gate, each of the semiconductor regions being capacitively coupled to the gate.
2. The memory cell of claim 1 wherein the memory cell is substantially isolated by shallow trench isolation.
3. The memory cell of claim 2 wherein the first and third semiconductor regions are P-type semiconductor and the second and fourth semiconductor regions are N-type semiconductors.
4. The memory cell of claim 1 wherein the first semiconductor region is doped more heavily than the third semiconductor region.