IP Library Granted Patent US 7,714,652
Granted Patent B2
US 7,714,652 · App. 12/098,847 · Granted May 11, 2010

Method for adjusting threshold voltage and circuit therefor

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Quick Facts
Patent No.
US 7,714,652
App. No.
12/098,847
Granted
May 11, 2010
Kind
B2
Abstract

A method and circuit for changing a threshold voltage of a transistor. The circuit includes a sense circuit coupled to a switching transistor, a circuit transistor and to one terminal of a resistor. The other terminal of the resistor is connected to a body contact. The switching transistor directs current along one of two different paths in response to an input voltage sensed by the sense circuit. When the switching transistor directs a first current along one path, the first current is steered towards the resistor and flows through the resistor in one direction and when the switching transistor directs a second current along the other path, the second current is directed towards the resistor and flows through the resistor in the opposite direction from the first current. Steering the currents varies the potential of a body with respect to the potential at the source of the circuit transistor.

Claims (22)

1. A method for changing a threshold voltage of a transistor, comprising varying a potential of a body region of a semiconductor material by steering one of a first current or a second current through a resistor in response to an input signal, wherein steering the one of the first current or the second current includes steering the first current in a first direction through the resistor in response to the input signal being greater than a reference signal and wherein steering the one of the first current or the second current includes steering the second current in a second direction through the resistor in response to the input signal being less than the reference signal.

2. The method of claim 1 , wherein the input signal is a common mode input voltage.

3. The method of claim 1 , wherein steering the one of the first current or the second current includes steering the first current in the first direction through the resistor in response to a common mode input signal being greater than the reference signal.

4. The method of claim 1 , wherein steering the one of the first current or the second current through the resistor includes decreasing a first voltage to be less than a second voltage in response to the input signal being greater than the reference signal.

5. The method of claim 1 , wherein steering the one of the first current or the second current through the resistor includes increasing a first voltage to be greater than a second voltage in response to the common mode input voltage being less than the reference signal.

6. The method of claim 1 , wherein steering the one of the first current or the second current through the resistor includes opening a switch to steer the one of the first current or the second current.

7. The method of claim 1 , wherein steering the one of the first current or the second current through the resistor includes closing a switch to steer the one of the first current or the second current.

8. The method of claim 1 , wherein steering the one of the first current or the second current through the resistor includes steering the second current through the resistor after amplifying a third current.

9. A circuit, comprising:

a differential pair of transistors, wherein each transistor of the differential pair of transistors has a source, a drain, and a gate, and wherein the sources of each transistor of the differential pair of transistors are commonly coupled together;

a body terminal;

first and second switches coupled to the commonly coupled sources;

first and second current sources coupled to the first and second switches, respectively;

third and fourth switches coupled to the body terminal of the circuit;

third and fourth current sources coupled to the third and fourth switches, respectively;

a common mode sense circuit coupled to the commonly coupled sources of the differential pair of transistors; and

a resistor coupled between the body terminal and the commonly coupled sources of the differential pair of transistors.

10. The circuit of claim 9 , further including a fifth current source coupled between a first source of operating potential and the commonly coupled sources.

11. The circuit of claim 9 , further including a load coupled to the drains of the differential pair of transistors, wherein the load is one of an active load or a passive load.

12. The circuit of claim 9 , wherein the common mode sense circuit comprises:

a transistor having a control electrode and first and second current carrying electrodes, the control electrode coupled for receiving a reference voltage and the first current carrying electrode coupled to the first current source through the first switch; and

a switch control circuit having a current sensing input, a first switch control output, and a second switch control output, the current sensing input coupled to the second current carrying electrode of the transistor, the first switch control output coupled to the first and third switches, and the second switch control output coupled to the second and fourth switches.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2008
From: MANGUDI, ARAVIND; JOSEPH, ERIC DAVID
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 020766/0646 →