Clock tree network in a field programmable gate array
View Patent ↗A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.
1. A clock tree distribution network for a field programmable gate array (FPGA) comprising:
a clock-source selector providing a root signal selected from at least one of an external clock signal, an internal clock signal and at least one phase lock loop cell output signal;
an array of programmable logic coupled to the clock-source selector, the logic array having a plurality of combinatorial logic modules having inputs and a plurality of sequential logic modules having clock inputs;
a hardwired clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and routes the selected signal to the clock inputs of the plurality of sequential logic modules in the array of programmable logic; and
a routed clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and routes the selected signal through at least one programmable element to at least one of the clock inputs of the plurality of sequential logic modules in the array of programmable logic.
2. The clock tree distribution network of claim 1 wherein the routed clock network further selects a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and routes the selected signal through at least one programmable element to at least one of the inputs of the combinatorial logic modules.
3. The clock tree distribution network of claim 1 wherein the internal clock signal is provided by a phase-locked loop circuit coupled to the clock-source selector.
4. The clock tree distribution network of claim 1 further comprising:
a plurality of I/O logic clusters; and
wherein the phase locked loop circuit is selectively coupleable to at least one of the plurality of I/O logic clusters.
5. The clock tree distribution network of claim 1 wherein the routed clock network routes the selected signal through a wiring track having programmable elements coupled to at least one of the clock inputs of the plurality of sequential logic modules in the array of programmable logic.
6. In a field programmable gate array including an array of programmable logic arranged as a plurality of core tiles, each core tile arranged into an array of logic clusters including a plurality of combinatorial logic modules having inputs and a plurality of sequential logic modules having clock inputs, a clock tree distribution network comprising:
at least one internal hardwired clock source;
at least one internal routed clock source;
a hardwired clock root center disposed in each core tile and coupled to the at least one internal hardwired clock source;
a routed clock root center disposed in each core tile and coupled to the at least one internal routed clock source;
a hardwired clock distribution circuit associated with each at least one internal hardwired clock source disposed in each core tile, each hardwired clock distribution circuit configured to select that a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and route the selected signal to the clock inputs of the plurality of sequential logic modules in the array of programmable logic in its core tile; and
a routed clock distribution circuit associated with each at least one internal routed clock source disposed in each core tile, each routed clock distribution circuit configured to select a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and route the selected signal through at least one programmable element to at least one of the clock inputs of the plurality of sequential logic modules in the array of programmable logic in its core tile.
7. The field programmable gate array of claim 6 wherein the routed clock distribution circuit associated with each at least one internal routed clock source disposed in each core tile is further configured to select a signal from at least one of the root signal, a local signal from the array of programmable logic, a positive power supply signal, and a ground signal and route the selected signal through at least one programmable element to at least one of the inputs of the plurality of combinatorial logic modules.
8. The field programmable gate array of claim 6 further comprising:
a plurality of I/O logic clusters; and
wherein the phase locked loop circuit is selectively coupleable to at least one of the plurality of I/O logic clusters.
9. The field programmable gate array of claim 6 wherein the internal clock signal is provided by a phase-locked loop circuit coupled to the clock-source selector.