Method of forming an oscillator circuit and structure therefor

1. An oscillator circuit of a power supply controller comprising:

a timing input configured to be coupled to a timing element;

a synchronization input operably coupled to receive a synchronization signal that has a first state and a second state wherein the synchronization input receives the synchronization signal from external to the oscillator circuit;

a first edge detector operably coupled to receive the synchronization signal and set an output of the first edge detector to a first state of the first edge detector responsively to the synchronization signal changing from the first state of the synchronization signal to the second state of the synchronization signal;

an oscillator configured to use the timing element to oscillate at a first frequency having a period and to form a clock signal having a first state and a second state during the period, the oscillator configured to restart the clock signal at the first state responsively to the synchronization signal transitioning from the first state of the synchronization signal to the second state of the synchronization signal during an interval where the clock signal is in the second state of the clock signal, and the oscillator configured to not restart the period responsively to the synchronization signal transitioning from the first state of the synchronization signal to the second state of the synchronization signal during an interval where the clock signal is in the first state of the clock signal; and

an output circuit operably coupled to receive the clock signal and force the synchronization input to the second state of the synchronization signal responsively to the clock signal transitioning from the second state of the clock signal to the first state of the clock signal.

2. The oscillator circuit of claim 1 wherein the output circuit includes a second edge detector coupled to receive the clock signal and an output follower coupled to receive an output of the second edge detector.

3. The oscillator circuit of claim 2 wherein a duration of an output signal of the first edge detector is less than a duration of the first state of the clock signal.

4. The oscillator circuit of claim 1 wherein the oscillator includes a latch operably coupled to a control circuit to form a first duration for the first state of the clock signal and to form a second duration for the second state of the clock signal.

5. The oscillator circuit of claim 4 wherein the control circuit includes a first current source operably coupled to charge a capacitor and form the first duration and a second current source operably coupled to discharge the capacitor and form the second duration.

6. The oscillator circuit of claim 4 wherein the latch has a first reset input coupled to receive the output of the first edge detector and to force the clock signal to the first state responsively to the output of the first edge detector.

7. The oscillator circuit of claim 6 wherein the first edge detector is configured to form a pulse responsively to the synchronization signal transitioning from the first state of the synchronization signal to the second state.

8. The oscillator circuit of claim 7 wherein the output circuit includes a second edge detector configured to form a pulse responsively to the clock signal transitioning from the second state of the clock signal to the first state.

9. The oscillator circuit of claim 8 wherein the output circuit includes an output follower configured to drive the synchronization input responsively to the pulse formed by the second edge detector.

10. A method of forming an oscillator circuit comprising:

configuring the oscillator circuit to oscillate at a first frequency having a period and to form a clock signal having first and second states during the period wherein the oscillator circuit is configured to be coupled to a timing element on a timing input and form the first frequency responsively to the timing element;

forming the oscillator circuit to receive a synchronization signal from external to the oscillator circuit wherein the synchronization signal has a first state and a second state wherein the synchronization signal is received on a synchronization input of the oscillator circuit;

configuring the oscillator circuit to restart the clock signal at the first state and to form the period at the first frequency responsively to the synchronization signal transitioning from the first state of the synchronization signal to the second state of the synchronization signal during an interval where the clock signal is in the second state of the clock signal; and

configuring the oscillator circuit to drive the synchronization input to the second state of the synchronization signal responsively to the clock signal transitioning from the second state of the period to the first state of the period.

11. The method of claim 10 wherein configuring the oscillator circuit to drive the synchronization input to the second state of the synchronization signal responsively to the clock signal has no effect on the clock signal.

12. The method of claim 10 wherein configuring the oscillator circuit to restart the clock signal at the first state includes configuring the oscillator circuit to not restart the clock signal responsively to the synchronization signal transitioning from the first state of the synchronization signal to the second state of the synchronization signal during an interval where the clock signal is in the first state of the clock signal.

13. The method of claim 10 wherein configuring the oscillator circuit to oscillate at the first frequency having the period includes coupling a latch to cause a control circuit to form a first time duration for the first state of the clock signal and to form a second time duration for the second state of the clock signal.

14. The method of claim 13 wherein forming the oscillator circuit to receive the synchronization signal includes operably coupling a positive edge detector to receive the synchronization signal and form an output having an active state representing a transition of the synchronization signal from the first state to the second state.

15. The method of claim 14 wherein operably coupling the positive edge detector includes coupling an output of the positive edge detector to reset the latch to cause the oscillator circuit to restart the clock signal at the first state.