IP Library Granted Patent US 7,821,063
Granted Patent B2
US 7,821,063 · App. 12/131,295 · Granted Oct 26, 2010

Semiconductor device having enhanced performance and method

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,821,063
App. No.
12/131,295
Granted
Oct 26, 2010
Kind
B2
Abstract

In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.

Claims (39)

1. A method for forming a semiconductor device, comprising the steps of:

providing a substrate having a major surface, wherein the substrate comprises a first conductivity type;

forming a pedestal structure on a portion of the major surface;

forming a conductive material along a side surface of the pedestal structure to define an edge of a first conduction electrode of the semiconductor device;

forming a first doped region of a second conductivity type in the major surface adjacent the first conduction electrode, wherein a portion of the first doped region forms a channel region when the semiconductor device is in operation;

forming second region of the first conductivity type in the first doped region; and

forming a localized region of doping of the first conductivity in the substrate in proximity to a drain edge of the channel region, wherein the localized region of doping is confined both vertically and horizontally adjacent the major surface, and wherein the localized region of doping has a dopant concentration at least five times greater than a dopant concentration of a portion of the semiconductor material, and wherein the portion of the semiconductor material is adjacent the major surface and adjacent to the localized region of doping.

2. The method of claim 1 , wherein the step of forming the localized region of doping includes forming a localized region of doping having a doping concentration about five times to about fifty times greater than that of the substrate.

3. The method of claim 1 , wherein the step of forming the localized region of doping includes ion implanting dopant into the substrate.

4. The method of claim 3 , wherein the step of ion implanting dopant includes ion implanting with a tilt angle between about 25 degrees and about 60 degrees.

5. The method of claim 1 , wherein the step of forming the localized region of doping includes forming the localized region of doping using an edge defined by the side surface of the pedestal structure.

6. A method for forming a semiconductor device, comprising the steps of:

providing a semiconductor material having a major surface, wherein the semiconductor material comprises a first conductivity type;

forming a body region of a second conductivity type opposite the first conductivity type as part of the semiconductor material, wherein the body region is configured to form a channel region;

forming a source region of the first conductivity type as part of the semiconductor material contiguous with the body region;

forming a control electrode formed in spaced relationship with the semiconductor material; and

forming a localized region of doping of the first conductivity type as part of the semiconductor material in proximity to a drain edge of the channel region, wherein the localized region of doping is confined both vertically and horizontally adjacent the major surface, and wherein the localized region of doping has a dopant concentration at least five times greater than a dopant concentration of a portion of the semiconductor material, and wherein the portion of the semiconductor material is adjacent the major surface and adjacent to the localized region of doping.

7. The method of claim 6 , wherein the step of forming the localized region of doping includes forming the localized region of doping extending a lateral distance from the body region in a range from about 0.1 microns and about 0.4 microns.

8. The method of claim 6 , wherein the step of forming the localized region of doping includes forming the localized region of doping having a dopant concentration about five times to about fifty times greater than that of the semiconductor material.

9. The method of claim 6 , wherein the step of providing the semiconductor material includes providing the semiconductor material having a second surface opposite the major surface, and wherein the method further includes the step of forming a conduction electrode associated with the second surface.

10. The method of claim 6 , further comprising the step of forming a pedestal structure associated with the major surface and having a side surface, wherein the step of forming the control electrode includes forming a conductive material along the side surface, and wherein the step of forming the localized region of doping includes forming the localized region of doping having an edge defined by the side surface of the pedestal structure.

11. The method of claim 10 , wherein the step of forming the pedestal structure includes the steps of:

forming a first dielectric layer associated with the major surface;

forming a second dielectric layer associated with the first dielectric layer; and

forming a conductive layer associated with the second dielectric layer and coupled to the control electrode.

12. The method of claim 11 , wherein the step of forming the conductive layer includes forming a conductive layer comprised of polycrystalline silicon.

13. The method of claim 6 , further comprising the step of forming a shield layer associated with the localized region of doping.

14. The method of claim 13 , wherein the step of forming the shield layer including forming a shield layer comprised of polycrystalline silicon.

15. A method of forming a semiconductor device, comprising the steps of:

providing a semiconductor substrate having a first layer of a first conductivity type and a major surface;

forming a body region of a second conductivity type opposite the first conductivity type associated with the first layer, wherein the body region is configured for forming a channel;

forming a source region of the first conductivity type associated with the body region;

forming a gate structure adjacent the channel; and

forming a current spreading region in a first portion of the first layer and abutting a drain end of the channel, wherein the current spreading region comprises the first conductivity type, and wherein the current spreading region is localized and confined both vertically and horizontally adjacent the major surface, and wherein the current spreading region has a dopant concentration at least five times greater than that of the first layer, and wherein a second portion of the first layer is adjacent the major surface, and wherein the current spreading region is between the body region and the second portion of the first layer.

16. The method of claim 15 , wherein the step of forming the current spreading region includes forming the current spreading region extending laterally from the body region a distance in a range from about 0.1 microns to about 0.4 microns.

17. The method of claim 15 further comprising the step of forming a pedestal structure in association with the major surface, and wherein the step of forming the gate structure includes forming a control electrode associated with a side surface of the pedestal structure.

18. The method of claim 17 wherein the step of forming the control electrode includes forming the control electrode further overlying the pedestal structure.

19. The method of claim 17 , wherein the step of forming the pedestal structure includes forming a pedestal structure having a shield layer.

20. The method of claim 15 , wherein the step of forming the current spreading region includes forming a current spreading region having a peak doping concentration in range from about 5.0×10 16 atoms/cm 3 to about 1.0×10 17 atoms/cm 3 .

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →