IP Library Granted Patent US 8,003,478
Granted Patent B2
US 8,003,478 · App. 12/134,401 · Granted Aug 23, 2011

Method of forming a bi-directional diode and structure therefor

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Quick Facts
Patent No.
US 8,003,478
App. No.
12/134,401
Granted
Aug 23, 2011
Kind
B2
Abstract

In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.

Claims (23)

1. A method of forming a bi-directional diode comprising:

forming a first doped region overlying a semiconductor region of a first conductivity type and a first doping concentration wherein the first doped region has a second conductivity type and a second doping concentration;

forming a second doped region of the first conductivity type within the first doped region;

forming a third doped region of the first conductivity type within the first doped region and spaced a first distance from the second doped region and having a third doping concentration wherein a differential doping concentration between the first doped region and the third doped region is greater than a differential doping concentration between the first doped region and the semiconductor region; and

reducing a recombination lifetime of carriers within the first doped region subsequently to forming the second and third doped regions.

2. The method of claim 1 wherein forming the first doped region includes forming the first doping concentration and the second doping concentration to have a differential doping concentration that is less than a differential doping concentration between the second and third doping concentrations.

3. The method of claim 2 wherein forming the second doped region includes forming the second doped region with the first conductivity type and a fourth doping concentration wherein a differential doping concentration between the second and fourth doping concentrations is greater than the differential doping concentration between the first and second doping concentrations.

4. The method of claim 3 wherein forming the third doped region includes forming the third doped region with an inner periphery that surrounds a periphery of the second doped region.

5. The method of claim 1 wherein forming the third doped region includes forming the third doped region no greater than about twenty five microns from the second doped region.

6. The method of claim 1 wherein reducing the carrier recombination lifetime within the first doped region includes irradiating the bi-directional diode with one of particle bombardment, an electron beam, a proton beam, a neutron beam, or gamma particles prior to assembling the bi-directional diode into a semiconductor package.

7. The method of claim 6 wherein irradiating the bi-directional diode includes irradiating the bi-directional diode at a dose of no less than 32 Kgy.

8. A method of forming a diode comprising:

providing a semiconductor substrate of a first conductivity type and a first doping concentration and having a surface;

forming a semiconductor region overlying at least a portion of the semiconductor substrate wherein the semiconductor region has a second conductivity type and a second doping concentration that is less than the first doping concentration;

forming a first diode within the semiconductor region including forming a first doped region within the semiconductor region and having a third doping concentration that forms a differential doping concentration with the semiconductor region that is greater than a differential doping concentration between the semiconductor substrate and the semiconductor region; and

reducing a carrier recombination lifetime within the first portion of semiconductor region.

9. The method of claim 8 further including forming a second diode in the semiconductor region and spaced a first distance from the first diode wherein a first portion of the semiconductor region forms a drift region for current flow between the first diode and the second diode; and wherein forming the first diode and forming the second diode includes forming a second portion of the semiconductor region underlying the first diode and having a thickness no greater than about twenty five microns, and forming a third portion of the semiconductor region underlying the first diode and having a thickness no greater than about twenty five microns.

10. A method of forming a diode comprising:

providing a semiconductor substrate of a first conductivity type and a first doping concentration and having a surface;

forming a semiconductor region overlying at least a portion of the semiconductor substrate wherein the semiconductor region has a second conductivity type and a second doping concentration that is less than the first doping concentration;

forming a first diode within the semiconductor region;

forming a second diode in the semiconductor region and spaced a first distance from the first diode wherein a first portion of the semiconductor region forms a drift region for current flow between the first diode and the second diode; and wherein forming the first diode and the second diode includes forming a first doped region within the semiconductor region and having the first conductivity type and a third doping concentration that is less than the second doping concentration, and forming a second doped region within the semiconductor region and having the first conductivity type and the third doping concentration; and

reducing a carrier recombination lifetime within the first portion of semiconductor region.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →