Subsampling wideband RSSI circuit
View Patent ↗A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.
1. A received signal strength indicator (RSSI) circuit comprising:
a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein said subsampling circuit subsamples said input signal, wherein said input signal is subsampled to concentrate a power in a narrow bandwidth, and wherein said subsampling circuit comprises:
a first switch and a first capacitor, wherein said first switch and said first capacitor are driven by an in-phase (I) sampling waveform; and
a second switch and a second capacitor, wherein said second switch and said second capacitor are driven by a quadrature (Q) sampling waveform;
an analog-to-digital converter (ADC) operatively connected to said subsampling circuit, wherein said ADC digitizes the subsampled signal; and
a baseband detector operatively connected to said ADC, wherein said baseband detector detects a power from the digitized subsampled signal and creates an output signal.
2. The RSSI circuit of claim 1 , wherein said first switch and said second switch comprise a transistor.
3. The RSSI circuit of claim 1 , wherein said baseband detector comprises any of a root mean square (RMS) (I 2 +Q 2 ) detector, and a peak detector.
4. The RSSI circuit of claim 1 , wherein said first switch and said second switch comprise a transmission gate.
5. The RSSI circuit of claim 1 , wherein said subsampling circuit and said ADC operate as a single subsampling ADC.
6. The RSSI circuit of claim 1 , further comprising ignoring higher order aliases at a multiple of said sampling frequency if said baseband detector is clocked at said sampling frequency.
7. An apparatus for detecting the power of an input signal, said apparatus comprising:
a memory unit comprising a set of computer programmable instructions;
a display unit operatively connected to said memory unit;
a processor that executes said computer programmable instructions;
a subsampling circuit that processes said input signal comprising a sampling frequency, fs, wherein said subsampling circuit subsamples said input signal, wherein said input signal is subsampled to concentrate a power in a narrow bandwidth, and wherein said subsampling circuit comprises:
a first switch and a first capacitor, wherein said first switch and first capacitor are driven by an in-phase (I) sampling waveform; and
a second switch and a second capacitor, wherein said second switch and second capacitor are driven by a quadrature (Q) sampling waveform;
an analog-to-digital converter (ADC) operatively coupled to said subsampling circuit, wherein said ADC digitizes the subsampled signal; and
a baseband detector operatively coupled to said ADC, wherein said baseband detector detects a power from the digitized subsampled signal and creates an output signal.
8. The apparatus of claim 7 , wherein said first switch and said second switch comprise a transistor.
9. The apparatus of claim 7 , wherein said first switch and said second switch comprise a transmission gate.
10. The apparatus of claim 7 , wherein said baseband detector comprises any of a root mean square (RMS) (I 2 +Q 2 ) detector, and a peak detector.
11. A method of detecting the power of an input signal comprising a sampling frequency, fs, integrated over a wide bandwidth in a received signal strength indicator (RSSI) circuit, said method comprising:
subsampling said input signal by a subsampling circuit to concentrate a power in a narrow bandwidth, wherein said input signal is subsampled over baseband frequencies range from DC to fs/2; and
detecting a power from said input signal based on the subsampled input signal,
wherein said subsampling circuit comprises a first switch and a first capacitor,
wherein said first switch and said first capacitor are driven by an in-phase (I) sampling waveform,
wherein said subsampling circuit comprises a second switch and a second capacitor, and
wherein said second switch and said second capacitor are driven by a quadrature (Q) sampling waveform.
12. The method of claim 11 , wherein first switch and said second switch comprise a transistor.
13. The method of claim 11 , wherein said power from said input signal is detected by a baseband detector.
14. The method of claim 11 , further comprising ignoring higher order aliases at a multiple of said sampling frequency if said baseband detector is clocked at said sampling frequency.
15. The method of claim 11 , further comprising filtering higher order aliases at a multiple of said sampling frequency.
16. The method of claim 13 , wherein said baseband detector comprises any of a root mean square (RMS) (I 2 +Q 2 ) detector, and a peak detector.
17. The method of claim 11 , further comprising using the detected power to set a gain of a programmable gain RF amplifier that precedes the RSSI circuit.
18. The method of claim 11 , wherein said first switch and said second switch comprise a transmission gate.
19. The method of claim 18 , further comprising using a gate input of said transmission gate as a sampling clock.
20. The method of claim 11 , further comprising digitizing the subsampled input signal.