IP Library Granted Patent US 7,871,861
Granted Patent B2
US 7,871,861 · App. 12/146,411 · Granted Jan 18, 2011

Stacked integrated circuit package system with intra-stack encapsulation

Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 7,871,861
App. No.
12/146,411
Granted
Jan 18, 2011
Kind
B2
Abstract

A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.

Claims (38)

1. A method for manufacturing a stacked integrated circuit package system comprising:

mounting a first integrated circuit over a first carrier;

mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect directly on the first carrier adjacent the first integrated circuit; and

forming an intra-stack encapsulation between the first carrier and the second carrier, surrounding the intra-stack interconnect and in an entire space between the first carrier and the second carrier, and the intra-stack encapsulation is the same thickness between the first carrier and the second carrier as the intra-stack interconnect.

2. The method as claimed in claim 1 wherein forming the intra-stack encapsulation between the first carrier and the second carrier includes molding the intra-stack encapsulation.

3. The method as claimed in claim 1 further comprising forming the second integrated circuit package system including:

mounting a second integrated circuit over the second carrier; and

forming a top encapsulation over the second integrated circuit and the second carrier.

4. The method as claimed in claim 1 wherein forming the intra-stack encapsulation between the first carrier and the second carrier includes molding an underfill.

5. A method for manufacturing a stacked integrated circuit package system comprising:

mounting a first integrated circuit over a first carrier;

connecting the first integrated circuit over the first carrier;

mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect directly on the first carrier adjacent the first integrated circuit;

forming an intra-stack encapsulation in an entire space between the first carrier and the second carrier surrounding the intra-stack interconnect, and the intra-stack encapsulation is the same thickness between the first carrier and the second carrier as the intra-stack interconnect; and

attaching an external interconnect below and to the first carrier.

6. The method as claimed in claim 5 further comprising forming the second integrated circuit package system having a top encapsulation not in contact with the intra-stack encapsulation.

7. The method as claimed in claim 5 wherein mounting the second integrated circuit package system over the first carrier and the first integrated circuit includes mounting the intra-stack interconnect adjacent to the first integrated circuit.

8. The method as claimed in claim 5 wherein forming the intra-stack encapsulation includes filling a space between the first carrier and the second carrier.

9. The method as claimed in claim 5 wherein attaching the external interconnect includes attaching solder ball.

10. A stacked integrated circuit package system comprising:

a first carrier;

a first integrated circuit over the first carrier;

a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect directly on the first carrier adjacent the first integrated circuit; and

an intra-stack encapsulation having characteristics of being formed between the first carrier and the second carrier and the intra-stack encapsulation surrounds the intra-stack interconnect and fills the entire space between the first carrier and the second carrier, and the intra-stack encapsulation is the same thickness between the first carrier and the second carrier as the intra-stack interconnect.

11. The system as claimed in claim 10 wherein the second integrated circuit package system having the second carrier with the intra-stack interconnect attached thereto includes the intra-stack interconnect below the second carrier.

12. The system as claimed in claim 10 wherein the intra-stack interconnect is between the first carrier and the second carrier.

13. The system as claimed in claim 10 wherein the second integrated circuit package system includes:

a second integrated circuit over the second carrier; and

a top encapsulation over the second integrated circuit and the second carrier.

14. The system as claimed in claim 10 wherein the intra-stack encapsulation includes an underfill.

15. The system as claimed in claim 10 wherein:

the first integrated circuit is connected with the first carrier; and

further comprising:

an external interconnect connected below and to the first carrier.

16. The system as claimed in claim 15 wherein the second integrated circuit package system includes a top encapsulation not in contact with the intra-stack encapsulation.

17. The system as claimed in claim 15 wherein the second integrated circuit package system over the first carrier and the first integrated circuit includes the intra-stack interconnect adjacent to the first integrated circuit.

18. The system as claimed in claim 15 wherein the intra-stack encapsulation fills a space between the first carrier and the second carrier.

19. The system as claimed in claim 15 wherein the external interconnect includes attaching solder ball.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2008
From: SONG, SUNGMIN; MYUNG, JUNWOO; JANG, BYOUNG WOOK
To: STATS CHIPPAC LTD.
Reel/Frame 021195/0924 →
Continuity (1)
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